54ACT112_09 Datasheet, PDF (1/8 Pages) National Semiconductor (TI) – Dual JK Negative Edge-Triggered Flip-Flop

54ACT112
OBSOLETE
July 20, 2009
Dual JK Negative Edge-Triggered Flip-Flop
General Description
The 'ACT112 contains two independent, high-speed JK flip-
flops with Direct Set and Clear inputs. Synchronous state
changes are initiated by the falling edge of the clock. Trigger-
ing occurs at a voltage level of the clock and is not directly
related to the transition time. The J and K inputs can change
when the clock is in either state without affecting the flip-flop,
provided that they are in the desired state during the recom-
mended setup and hold times relative to the falling edge of
the clock. A LOW signal on S_D or C_D prevents clocking and
forces Q or Q HIGH, respectively. Simultaneous LOW signals
on S_D and C_D force both Q and Q HIGH.
Asynchronous Inputs:
LOW input to S_D sets Q to HIGH level
LOW input to C_D sets Q to LOW level
Clear and Set are independent of clock
Simultaneous LOW on C_D and S_D makes both Q and Q
HIGH
Features
■ ^{'ACT112 has TTL-compatible inputs}
■ ^{Outputs source/sink 24 mA}
■ ^{Standard Microcircuit Drawing (SMD) 5962-8995001}
Connection Diagrams
Pin Assigment for
DIP and Flatpack
Pin Descriptions
Pin Names
J₁, J₂, K₁, K₂
CP₁, CP₂
C_D1, C_D2
S_D1, S_D2
Q₁, Q₂, Q₁, Q₂
Description
Data Inputs
Clock Pulse Inputs
(Active Falling Edge)
Direct Clear Inputs (Active LOW)
Direct Set Inputs (Active LOW)
Outputs
10097603
Pin Assigment
for LCC
10097605
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© 2009 National Semiconductor Corporation 100976
100976 Version 2 Revision 2 Print Date/Time: 2009/07/20 16:20:36
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