54AC273 Datasheet, PDF (1/8 Pages) National Semiconductor (TI) – Octal D Flip-Flop

July 1998
54AC273
Octal D Flip-Flop
General Description
The ’273 has eight edge-triggered D-type flip-flops with indi-
vidual D inputs and Q outputs. The common buffered Clock
(CP) and Master Reset (MR) input load and reset (clear) all
flip-flops simultaneously.
The register is fully edge-triggered. The state of each D in-
put, one setup time before the LOW-to-HIGH clock transi-
tion, is transferred to the corresponding flip-flop’s Q output.
All outputs will be forced LOW independently of Clock or
Data inputs by a LOW voltage level on the MR input. The de-
vice is useful for applications where the true output only is re-
quired and the Clock and Master Reset are common to all
storage elements.
Features
n Ideal buffer for microprocessor or memory
n Eight edge-triggered D flip-flops
n Buffered common clock
n Buffered, asynchronous master reset
n See ’377 for clock enable version
n See ’373 for transparent latch version
n See ’374 for TRI-STATE^® version
n Outputs source/sink 24 mA
n ’ACT has TTL-compatible inputs
n Standard Military Drawing (SMD)
— ’AC273: 5962-87756
Logic Symbols
IEEE/IEC
DS100288-1
Pin Names
D₀– D₇
MR
CP
Q₀– Q₇
Description
Data Inputs
Master Reset
Clock Pulse Input
Data Outputs
DS100288-2
TRI-STATE^® is a registered trademark of National Semiconductor Corporation.
FACT™ is a trademark of National Semiconductor Corporation.
© 1998 National Semiconductor Corporation DS100288
PrintDate=1998/07/27 PrintTime=08:02:05 44014 ds100288 Rev. No. 1 cmserv Proof
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