54AC109 Datasheet, PDF (1/8 Pages) National Semiconductor (TI) – Dual JK Positive Edge-Triggered Flip-Flop

August 1998
54AC109 • 54ACT109
Dual JK Positive Edge-Triggered Flip-Flop
General Description
The ’AC/’ACT109 consists of two high-speed completely in-
dependent transition clocked JK flip-flops. The clocking op-
eration is independent of rise and fall times of the clock
waveform. The JK design allows operation as a D flip-flop
(refer to ’AC/’ACT74 data sheet) by connecting the J and K
inputs together.
Asynchronous Inputs:
LOW input to S_D (Set) sets Q to HIGH level
LOW input to C_D (Clear) sets Q to LOW level
Clear and Set are independent of clock
Simultaneous LOW on C_D and S_D makes both Q and Q
HIGH
Features
n I_CC reduced by 50%
n Outputs source/sink 24 mA
n ’ACT109 has TTL-compatible inputs
n Standard Military Drawing (SMD)
— ’AC109: 5962-89551
— ’ACT109: 5962-88534
Logic Symbol
IEEE/IEC
DS100267-1
DS100267-2
DS100267-7
Pin Names
J₁, J₂, K₁, K₂
CP₁, CP₂
C_D1, C_D2
S_D1, S_D2
Q₁, Q₂, Q₁, Q₂
Description
Data Inputs
Clock Pulse Inputs
Direct Clear Inputs
Direct Set Inputs
Outputs
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© 1998 National Semiconductor Corporation DS100267
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