54174 Datasheet, PDF (1/8 Pages) National Semiconductor (TI) – Hex/Quad D Flip-Flops with Clear

June 1989
54174 DM54174 DM74174 54175 DM54175 DM74175
Hex Quad D Flip-Flops with Clear
General Description
These positive-edge triggered flip-flops utilize TTL circuitry
to implement D-type flip-flop logic All have a direct clear
input and the quad (175) version features complementary
outputs from each flip-flop
Information at the D inputs meeting the setup and hold time
requirements is transferred to the Q outputs on the positive-
going edge of the clock pulse Clock triggering occurs at a
particular voltage level and is not directly related to the tran-
sition time of the positive-going pulse When the clock input
is at either the high or low level the D input signal has no
effect at the output
Features
Y _{174 contains six flip-flops with single-rail outputs}
Y _{175 contains four flip-flops with double-rail outputs}
Y _{Buffered clock and direct clear inputs}
Y _{Individual data input to each flip-flop}
Y _{Applications include}
Buffer storage registers
Shift registers
Pattern generators
Y _{Typical clock frequency 40 MHz}
Y _{Typical power dissipation per flip-flop 38 mW}
Y _{Alternate Military Aerospace device (54174 54175) is}
available Contact a National Semiconductor Sales Of-
fice Distributor for specifications
Connection Diagrams
Dual-In-Line Package
Dual-In-Line Package
TL F 6557 – 1
Order Number 54174DMQB 54174FMQB DM54174J
DM54174W or DM74174N
See NS Package Number J16A N16E or W16A
TL F 6557 – 2
Order Number 54175DMQB 54175FMQB DM54175J
DM54175W or DM74175N
See NS Package Number J16A N16E or W16A
Function Table (Each Flip-Flop)
C1995 National Semiconductor Corporation
Inputs
Outputs
Clear
Clock
D
Q
Q
L
X
X
L
H
H
u
H
H
L
H
u
L
L
H
H
L
X
Q₀
Q₀
H e High Level (steady state)
L e Low Level (steady state)
X e Don’t Care
u e Transition from low to high level
Q₀ e The level of Q before the indicated steady-state input conditions were established
e 175 only
TL F 6557
RRD-B30M105 Printed in U S A