100355 Datasheet, PDF (1/10 Pages) National Semiconductor (TI) – Low Power Quad Multiplexer/Latch

August 1998
100355
Low Power Quad Multiplexer/Latch
General Description
The 100355 contains four transparent latches, each of which
can accept and store data from two sources. When both En-
able (E_n) inputs are LOW, the data that appears at an output
is controlled by the Select (S_n) inputs, as shown in the Oper-
ating Mode table. In addition to routing data from either D₀ or
D₁, the Select inputs can force the outputs LOW for the case
where the latch is transparent (both Enables are LOW) and
can steer a HIGH signal from either D₀ or D₁ to an output.
The Select inputs can be tied together for applications re-
quiring only that data be steered from either D₀ or D₁. A
positive-going signal on either Enable input latches the out-
puts. A HIGH signal on the Master Reset (MR) input over-
rides all the other inputs and forces the Q outputs LOW. All
inputs have 50 kΩ pulldown resistors.
Features
n Greater than 40% power reduction of the 100155
n 2000V ESD protection
n Pin/function compatible with 100155
n Voltage compensated operating range = −4.2V to −5.7V
n Standard Microcircuit Drawing
(SMD) 5962-9165401
Logic Symbol
Pin Names
E₁, E₂
S₀, S₁
MR
D_na– D_nd
Q_a– Q_d
Q_a– Q_d
Connection Diagrams
24-Pin DIP
DS100294-1
Description
Enable Inputs (Active LOW)
Select Inputs
Master Reset
Data Inputs
Data Outputs
Complementary Data Outputs
24-Pin Quad Cerpak
DS100294-2
© 1998 National Semiconductor Corporation DS100294
DS100294-3
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