100315 Datasheet, PDF (1/6 Pages) National Semiconductor (TI) – Low-Skew Quad Clock Driver

August 1998
100315
Low-Skew Quad Clock Driver
General Description
The 100315 contains four low skew differential drivers, de-
signed for generation of multiple, minimum skew differential
clocks from a single differential input. This device also has
the capability to select a secondary single-ended clock
source for use in lower frequency system level testing. The
100315 is a 300 Series redesign of the 100115 clock driver.
n Differential inputs and outputs
n Secondary clock available for system level testing
n 2000V ESD protection
n Voltage compensated operating range: −4.2V to −5.7V
n Standard Microcircuit Drawing
(SMD) 5962-9469601
Features
n Low output to output skew (≤50 ps)
Logic Diagram
Connection Diagram
Flatpak
DS100319-1
Pin Names
CLKIN, CLKIN
CLK_1–4, CLK_1–4
TCLK
CLKSEL
Description
Differential Clock Inputs
Differential Clock Outputs
Test Clock Input (Note 1)
Clock Input Select (Note 1)
Note 1: TCLK and CLKSEL are single-ended inputs, with internal 50 kΩ pull-
down resistors.
Truth Table
DS100319-2
CLKSEL CLKIN
L
L
L
H
H
X
H
X
L = Low Voltage Level
H = High Voltage Level
X = Don’t Care
CLKIN
H
L
X
X
TCLK
X
X
L
H
CLK_N
L
H
L
H
CLK_N
H
L
H
L
© 1998 National Semiconductor Corporation DS100319
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