SM8577B Datasheet, PDF (9/10 Pages) Nippon Precision Circuits Inc – Real-time Clock IC

Data Read
SM8577B
CE
CLK
DATA
123
8 9 10 11
58 59 60
60+n
Don't Care
Control Bits
Data Input Mode
Output data
not change
s1 s2 s4
y20 y40 y80
Second
Year
Data Output Mode
When CE is HIGH, data read mode starts from the
first rising edge of CLK for which DATA is LOW.
Valid data is then output on DATA from the 9th
rising edge of CLK. Time and date data is loaded
into the shift register on the 8th falling edge of CLK
and then output on DATA in sync with the rising
edge of CLK, starting with the seconds’ digit LSB.
Data is loaded and shifted in the sequence second,
minute, hour, week, day, and month. The output data
is valid for the first 60 rising edges of CLK. Output
data does not change after the 60th rising edge, even
if clock input continues.
Within the 60 cycles of valid data output, partial data
output can be obtained by taking CE LOW after the
Data Write
corresponding number of cycles. For example, if
only the ‘second’ to ‘week’ data output is required,
then that data only is output if CE goes LOW after 36
clock cycles.
For continuous data reads, a wait time (t_RCV) is
required before the next data cycle after CE goes
LOW.
Note that if a timer counter update operation (a 1 s
carry) occurs during a data read cycle, the data in the
shift register is not updated and, as a result, the
output data contains an error of −1 s.
The data read cycle should be completed within
t_CE ≤ 0.9 s.
CE
CLK
123
8 9 10 11
58 59 60
60+n
DATA
Don′t Care
Control Bits
Data Input Mode
s1 s2 s4
y20 y40 y80
Second
Year
Data Input Mode
NIPPON PRECISION CIRCUITS—9