NR8576AA Datasheet, PDF (9/10 Pages) Nippon Precision Circuits Inc – Real-time Clock Modules

Data Read
CLK
123
CE
WR
NR8576 Series
52 53 54
54+n
DATA
OUTPUT MODE
S1 S2 S4 S8 S10 S20 S40 FDT
second
Data is output when WR is LOW and CE is HIGH.
Time and calendar data is loaded into shift registers
on the first rising edge of the clock CLK, and the sec-
onds’ digit LSB is output on DATA.
The data is then loaded and shifted in the sequence
second, minute, hour, week, day, and month on the
rising edge of CLK, and output on DATA. The output
data is valid after 52 rising edges of the clock; data
input after 52 cycles does not alter the first 52 bits of
valid data.
y8 y10 y20 y40 y80
year
NON CHANGE
OUTPUT DATA
Within the 52 cycles of valid data, data already input
can be output if there is a falling edge of CE after the
corresponding number of cycles. For example, the
data comprising the second-to-week is output is CE
goes LOW after 28 clock cycles.
For continuous data reads, a wait time (t_RCV) is
required before the next data cycle if CE has gone
LOW.
Note that if an update operation (a 1 s carry) occurs
during a data read, an error of −1 s in the read data is
generated.
The data read time should be completed after
t_CE ≤ 0.9 s.
NIPPON PRECISION CIRCUITS—9