CF5762AB0 Datasheet, PDF (5/10 Pages) Nippon Precision Circuits Inc – Analog Chime Clock CMOS IC

CF5762AB0
FUNCTIONAL DESCRIPTION
Motor Output
Sweep movement frequency: 8Hz
The pulse cycle (T_cy) and the pulsewidth (T_pw) correspond to 1/16 Sec (= 62.5ms).
Tpw
O1
Tcy
Tcy
O2
Tpw
VDD
VSS
VDD
VSS
Figure 1. Motor pulse output
Reset
All functions are reset when RESET goes HIGH.
The reset is released when RESET goes LOW or
open circuit (RESET has a built-in pull-down resis-
tor).
Clock movement reset
For step clock movement, the seconds are stopped.
When reset is released, the next pulse is output on
the opposing output pin to that immediately before
the reset was applied. The time delay until the pulse
output after reset is released is 1 ^{+ 0.0625} seconds.
–0
For sweep clock movement, both outputs O1 and O2
are held HIGH during reset.
Melody reset
If a reset occurs during melody or chime output, the
output stops immediately. During reset, the MT is
valid when it is input. When the MT pin is HIGH, the
reset signal is valid if input.
Time reset
During the timing between reset and the hourly sig-
nal input when the melody select pins (SEL1, SEL2)
are used to monitor, chime monitoring is inactive
while melody monitoring is active.
NIPPON PRECISION CIRCUITS INC.—5