SM6802A Datasheet, PDF (2/15 Pages) Nippon Precision Circuits Inc – Class-D Stereo Amplifier for Portable Device

BLOCK DIAGRAM
SM6802A
LEQP LEQN TESTN DRCN PWDN MUTEN
VDD3
LIN
VREF1
RIN
REQP
REQN
−
+
−
+
BIAS
VREF
−
+
−
+
PWM
Modulator
LEVEL SHIFTER
BUFFER
LEVEL SHIFTER
BUFFER
OSC
MUTE,POWERDOWN,
PROTECTION
PWM
Modulator
LEVEL SHIFTER
BUFFER
LEVEL SHIFTER
BUFFER
VSS1 VDD1
VDD2
LOUTP
LOUTN
VSS2
ROUTP
ROUT
PIN DESCRIPTION
Number
Name ^*1
I/O^*2
Function
1
LEQP
I
Lch equalizer network connection
2
LIN
I
Lch signal input
3
VDD1
–
Supply (input system)
4
RIN
I
Rch signal input
5
REQP
I
Rch equalizer network connection
6
REQN
I
Rch equalizer network connection
7
VSS1
–
Ground (input system)
8
PDWN
I
Power-down control (active LOW)
9
DRCN
I
Dynamic range compression mode setting (HIGH: normal operation, LOW: compression mode)
10
ROUTN
O
Rch speaker minus (–) output
11
VDD2
–
Supply (output stage)
12
ROUTP
O
Rch speaker plus (+) output
13
VSS2
–
Ground (output stage)
14
LOUTP
O
Lch speaker plus (+) output
15
VDD3
–
Supply (output stage)
16
LOUTN
O
Lch speaker minus (–) output
17
MUTEN
I
Mute control (active LOW)
18
TESTN
Ip
Test pin (HIGH: normal operation, LOW: test mode)
19
VREF1
–
Reference voltage 1 (bias voltage)
20
LEQN
O
Lch equalizer network connection
*1. V_DDS = VDD1, V_DDP = VDD2 = VDD3, V_SS = VSS1 = VSS2
*2. Ip = input pin with built-in pull-up resistor
NIPPON PRECISION CIRCUITS INC.—2