SM6801A Datasheet, PDF (2/16 Pages) Nippon Precision Circuits Inc – Class-D Mono Amplifier for Portable Device

BLOCK DIAGRAM
SM6801A
EQP
EQN
DRCN MUTEN
TESTN
PDWN
VDD4
IN
−
+
−
+
VREF1
BIAS
VREF
PWM
Modulator
LEVEL
SHIFTER
BUFFER
LEVEL
SHIFTER
BUFFER
OSC
MUTE,
POWER DOWN,
PROTECTION
OUTP
VSS2
OUTN
VSS1 VDD1 VDD2
VDD3
PIN DESCRIPTION
Number
Name ^*1
I/O^*2
Function
1
DRCN
I
Dynamic range compression mode setting (HIGH: normal operation, LOW: DRC mode)
2
VDD1
–
Supply (input system)
3
VREF1
–
Reference voltage 1 (bias voltage)
4
IN
I
Signal input
5
EQP
I
Equalizer network connection
6
EQN
I
Equalizer network connection
7
VSS1
–
Ground (input system)
8
TESTN
Ip
Test pin (HIGH: normal operation, LOW: test mode)
9
VDD3
I
Supply (OUTN stage)
10
OUTN
O
Speaker minus (–) output
11
VSS2
–
Ground (output stage)
12
OUTP
O
Speaker plus (+) output
13
VDD4
–
Supply (OUTP stage)
14
PDWN
I
Power-down control (active LOW)
15
VDD2
–
Supply (logic system)
16
MUTEN
I
Mute control (active LOW)
*1. V_DDS = VDD1, VDD2, V_DDP = VDD3, VDD4, V_SS = VSS1, VSS2
*2. Ip = input pin with built-in pull-up resistor
SEIKO NPC CORPORATION —2