NR8576 Datasheet, PDF (2/11 Pages) Nippon Precision Circuits Inc – Real-time Clock Modules

BLOCK DIAGRAM
NR8576 series
32.768kHz
OSC
VDD VSS
Divider
Timer Counter
FOUT
FSEL
FOE
DATA
CLK
WR
CE
Output
Controller
I/O
Controller
Voltage
Detect
Shift Register
Control
Circuit
PIN DESCRIPTION
Name
VSS
CE
FSEL
WR
FOE
VDD
CLK
DATA
FOUT
NC
I/O
Description
–
Ground
Connect a ≥ 0.1µF capacitor between VDD and VSS.
Chip enable.
I
HIGH: Enable
LOW: DATA goes high impedance; input on WR, CLK, and DATA stops; and the TM bit is cleared.
FOUT output frequency select.
I
HIGH: 1Hz
LOW: 32.768kHz
DATA input/output control switch.
I
HIGH: Data input mode (RTC write)
LOW: Data output mode (RTC read)
FOUT output enable control.
I
HIGH: The frequency selected by FSEL is output on FOUT.
LOW: FOUT goes high impedance.
–
Supply voltage.
Connect a ≥ 0.1µF capacitor between VDD and VSS.
I
System clock input.
Data is input (RTC write mode) and output (RTC read mode) on the rising edge of CLK.
I/O
Data read and write input/output
Frequency output (output controlled by FOE and frequency selected by FSEL).
O
In 1Hz output mode, the 1Hz signal is synchronized to the internal 1 second signal.
FOUT output is not affected by the CE signal.
–
No connection. Leave open for normal use.
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