SM5879AV Datasheet, PDF (12/20 Pages) Nippon Precision Circuits Inc – 3rd-order , 2-channel D/A Converter

SM5879AV
FUNCTIONAL DESCRIPTION
System Clock
Note that the input clock accuracy and jitter greatly
influence the AC analog characteristics.
The system clock can be controlled by a crystal oscil-
lator consisting of a crystal connected between XTI
and XTO and a built-in CMOS invertor or, alterna-
System Reset (RSTN)
System reset for SM5879AV is performed by a built-
in power ON reset circuit.
At system reset, the internal arithmetic operation and
output timing counter are synchronized with the next
LCRI rising edge and thereby reset again for syn-
chronization with external elements.
tively, an external system clock. Since the built-in
CMOS invertor has a feedback resistor, the external
system clock can be AC coupled to XTI. The system
clock is output from CKO.
Analog output is muted by this resetting, and muting
is cleared by the ninth LCRI rise (See Figure 1).
However, noise is generated due to the change in
PWM output during a timing reset. An external mute
circuit is necessary to prevent this noise.
Power on Switch
LRCI
Internal
Reset
LO
RO
1
2
3
9 10
Output Muted
Figure 2. System reset timing
Audio Data Input (DI, BCKI, LRCI)
The digital audio data is input on DI in MSB-first, 2s- The bit clock frequency on BCKI should be between
complement, 16-bit serial format.
32fs and 64fs.
Serial data bits are read into the SIPO register (serial-
to-parallel converter register) on the rising edge of the
bit clock BCKI.
LRCI
BCKI
(MAX64fs)
DI
1 / fs
Lch
16bit
Rch
16bit
MSB
LSB
MSB
LSB
Figure 3.
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