SM5878AM Datasheet, PDF (12/16 Pages) Nippon Precision Circuits Inc – 3rd-order , 2-channel D/A converter

SM5878AM/AV
FUNCTIONAL DESCRIPTION
System Clock/Speed Switching (XTI, XTO, CKO, DS)
The system clock on XTI can be set to run at one of
two speeds, 384fs (normal speed) or 192fs (double-
speed), where fs is the input frequency on LRCI. The
speed for CD playback is set by the input level on
DS, as shown in table 1. The system clock should be
fixed at 16.9344 MHz.
Table 1. System clock select
Parameter
Symbol
DS
LOW
(normal
speed)
HIGH
(double
speed)
Note that the input clock accuracy and signal-to-
noise ratio greatly influence the AC analog
characteristics.
The system clock can be controlled by a crystal
oscillator comprising a crystal connected between
XTI and XTO and the built-in CMOS inverter.
Alternatively, an external system clock can be input
on XTI. As the internal CMOS inverter has a
feedback resistor, the external clock can be AC
coupled to XTI. The system clock is output on CKO.
XTI input clock
frequency
CD playback XTI
frequency
f_XI
(= 1/t_XI)
f_XI
384fs
16.9344 MHz
at fs = 44.1
kHz
192fs
16.9344 MHz
at fs = 88.2
kHz
CKO output clock
frequency
f_CO
384fs
192fs
Internal system
clock period
T_SYS
t_XI
t_XI
System Reset (RSTN)
The device should be reset in the following cases.
s At power ON
s When LRCI and/or the system clock XTI stop, or
other abnormalities occur.
The device is reset by applying a LOW-level pulse on
RSTN. At system reset, the internal arithmetic
operation and output timing counter are synchronized
on the next LRCI rising edge, as shown in figure 1.
RSTN
LRCI
LOW
1
2
3
9
10
Internal reset
LO
Outputs muted
RO
Figure 1. System reset timing
Audio Data Input (DI, BCKI, LRCI)
The digital audio data is input on DI in MSB-first, 2s-
complement, 16-bit serial format.
Serial data bits are read into the SIPO register (serial-
to-parallel converter register) on the rising edge of the
bit clock BCKI.
The arithmetic operation and output timing are
independent of the input timing. Accordingly, after a
reset, as long as the clock frequency ratio between
LRCI and the system clock XTI is maintained, phase
differences between LRCI, BCKI and the system
clock XTI do not affect the functional operation. Also,
any jitter present on the data input clock does not
appear as output pulse jitter.
The bit clock frequency on BCKI should be between
32fs and 64fs.
NIPPON PRECISION CIRCUITS—12