SM5865CM Datasheet, PDF (12/20 Pages) Nippon Precision Circuits Inc – D/A Converter for Digital Audio

SM5865CM
VBA, VBB
A 0.5VDD signal is output from VBA, VBB using a resistor divider network. Using these pins allows the use
of the SM5865CM to replace the pin-compatible SM5865BM product.
31 Level
DEM DAC
31 Level
DEM DAC
SM5865CM
31 Level
DEM DAC
31 Level
DEM DAC
RA
IOUTA
VBA
RB
IOUTB
VBB
Figure 10. VBA, VBB
Audio Data Input (DI, BCKI, WCKI, IWSL)
I Input data format
The audio data is input in MSB-first, 2s-complement, 24-bit/20-bit serial format. The input word bit length is
selected by IWSL, 24-bit when HIGH, and 20-bit when LOW.
I Jitter-free function
The SM5865CM serial input data from DI synchronize with the word clock (WCKI) and are read into the first
register stage, and those also synchronize with the clock derived from divided system clock and are read into
the next register stage. This word clock and the system clock are always phase compared. When a phase shift
was detected, the comparison result is used to perform input timing adjustment in the system clock. Therefore
this process enable internal calculations not to be affected by generated large jitter on the word clock or chang-
ing the sampling rate during inputting data.
System Clock Divider (CKDVN)
The SM5865CM has a built-in clock frequency divider. The divider enables the internal system clock to oper-
ate at half the input frequency, for example when the external system clock input frequency is high.
System Reset (RSTN)
The device should be reset in the following cases.
I At power ON
I When the system clock CKI stops, or other abnormalities occur.
The device is reset by applying a LOW-level pulse on RSTN.
NIPPON PRECISION CIRCUITS—12