SM8701BM Datasheet, PDF (10/14 Pages) Nippon Precision Circuits Inc – DVD Player Clock Generator

SM8701BM
Operation Control
The SM8701BM functions are controlled by inputs
MLEN/R2 (pin 1), MDT/R0 (pin 19) and MCK/R1
(pin 20). The operating mode is selected by input P/S
(pin 2)—serial control when P/S is LOW, and paral-
lel control when P/S is HIGH. Table 2 shows the
relationship between functions and mode.
Table 2. Control functions
Function
Sampling frequency group: 48/44.1/32 kHz
Sampling rate: standard/double
Clock output: enable/disable
Controllable
Serial Parallel
Yes
Yes
Yes
Yes
Yes
No
Serial control (P/S = LOW)
When P/S is LOW, the control interface is serial con-
trol mode. The serial control data is set by 16-bit
MDT data in sync with the MCK clock and the
MLEN enable signal clock at the serial control
mode. The format is shown in figure 4.
MCK
MDT D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
MLEN
Figure 4. Serial control format
The 16-bit mode register (MREG) is shown in figure
5, and the name and function of each bit is described
in tables 3 to 5. In serial control mode, mode register
bits D15 to D10 must be set to 011100. D3 is fixed as
LOW.
MREG 0 1 1 1 0 0 CE6 CE5 CE4 CE3 CE2 CE1 RSV R2 R1 R0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Figure 5. Mode register
Note: RSV is fixed as LOW .
Table 3. Mode register control bit functions
Table 4. CE6 to CE1 clock output control setting
Bit
D9
D8
D7
D6
D5
D4
D3
D2/D1/D0
Name
CE6
CE5
CE4
CE3
CE2
CE1
RSV
R2/R1/R0
Function
M O N output enable/disable
MO output enable/disable
SO4 output enable/disable
SO3 output enable/disable
SO2 output enable/disable
SO1 output enable/disable
Fixed as LOW
Sampling frequency select
CE6 to CE1
LOW
HIGH
Clock output
Disable (LOW -level output)
Enable (default)
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