MTP5N05 Datasheet, PDF (1/2 Pages) New Jersey Semi-Conductor Products, Inc. – N-CHANNEL ENHANCEMENT MODE SILICON GATE

'/£Ti£iy <z~>£.m.i-(-onaiicto'i lJ 10ducts., Line.
tx
U
20 STERN AVE.
SPRINGFIELD, NEW JERSEY 07081
U.S.A.
I)t'sii;iH'i-'> Data Sheet
N-CHANNEL ENHANCEMENT MODE SILICON GATE
TMOS POWER FIELD EFFECT TRANSISTOR
These TMOS Power RETs are designed for low voltage, high
speed power switching applications such as switching regulators,
converters, solenoid and relay drivers.
• Silicon Gate for Fast Switching .Speeds — Switching Times
Specified at 100°C
• Designer's Data — IQSS. vOS(on). VQs(th) and SOASpecified at
Elevated Temperature
• Rugged — SOA is Power Dissipation Limited
• Source-to-Orain Dioda Characterized for Use With
Inductive Loads
MTP4N08, MTP5N05
MTP4N10, MTP5N06
4.0 and 5.0 AMPERE
N-CHANNEL TMOS
POWER FET
rOS(on) 3 0-« OHM
80 and 100 VOLTS
SO ind 60 VOLTS
TMOS
os
MAXIMUM RATINGS
1
Rating
Symbol
. Drain-Source Voltage
Drain-Gate Voltage
|HGS - 1.0 MO)
Gate-Soure* VoHage
Drain Currant
Continuous
Pulsed
Gale Current — Pulsed
Total Power
Dissipation @ T(; = 2S°C
Derate above 25°C
Operating and Storage
Temparaturn Rango
VOSS
VOGH
VGS
ID
'DM
'CM
PO
Tj.Tstg
THERMAL CHARACTERISTICS
Thermal Resistance
Junction to Case
«9JC
Maximum Lead Tamp, for
TL
Soldering Purposes. 1/8*
from case for 5 seconds
5N05
50
SO
MTP
SNOB 4N08
60
80
60
80
4N10
100
100
±20
50
40
10
90
15
50
04
-65 to 1 50
2.5
275
Unit
Vdc
Vdc
V*
Adc
Adc
Warn
W/°C
°C
°C/W
°C
"Wont Cuv" Condition*
The Designer's Data Sheet permits the design of most circuits entirely from the
i nformation presented. Limit data — representing device characteristics boundaries—are
given to facilitate "worst casa" design.
Quality Semi-Conductors
MTP4NO*
MTMN10
M1F5NOS
MIP5N06
•uuifnn
m
a ^1M
la
TO-220A8