NJU26209 Datasheet, PDF (7/10 Pages) New Japan Radio – DAEP Decoder

NJU26209
I²C Bus
When the NJU26209 is configured for I²C bus communication in SEL=”Low”, the serial host interface transfers
data on the SDA pin and clocks data on the SCL pin. The SDA is an open drain pin requiring a pull-up resistance.
Pins AD1 and AD2 are used to configure the seven-bit SLAVE address of the serial host interface. (Table 6)
Table 6 I²C Bus Interface Slave address
bit7
bit6
bit5
0
0
1
0
0
1
0
0
1
0
0
1
AD2
AD1
R/W
bit4
bit3
bit2
bit1
bit0
1
1
0
0
1
1
0
1
R/W
1
1
1
0
1
1
1
1
Start
bit
Slave Address ( 7bit )
R/W
bit
ACK
* SLAVE address is 0 when AD1/2 is “Low”. SLAVE address is 1 when AD1/2 is “High”.
* SLAVE address is 0 when R/W is “W”. SLAVE address is 1 when R/W is “R”.
Note:
Both “Standard-Mode (100kbps)” and “Fast-Mode (400kbps)” data transfer rate are supported.
4-Wire Serial Interface
The serial host interface can be configured for 4-Wire Serial bus communication by setting SEL1=”High” during the
Reset Sequence initialization. SHI bus communication is full-duplex; a write byte is shifted into the SDIN pin at the
same time that a read byte is shifted out of the SDOUT pin.
Data transfers are MSB first and are enabled by setting SSb = “Low”. Data is clocked into SDIN on rising
transitions of SCK. Data is latched at SDOUT on falling transitions of SCK except for the first byte(MSB) which is
latched on the falling transitions of SSb. SDOUT is always CMOS output. SDOUT does not require a pull-up
resistance.
SSb
SCK
SDIN
bit7 _{bit6 bit5}
MSB
SDOUT ^unstable bit7 bit6 bit5
bit1 bit0
LSB
bit1 bit0
unstable
Fig. 4 4-Wire Serial Interface Timing
Note :
When the data-clock is less than 8 clocks, the input data is shifted to LSB side and is sent to the DSP core at the
transition of SSb=”High”.
When the data-clock is more than 8 clocks, the last 8 bit data becomes valid.
After sending LSB data, SDOUT transmits the MSB data which is received via SDIN until SSb becomes “High”.
Ver.2008-12-04
-7-