NJU6678 Datasheet, PDF (31/45 Pages) New Japan Radio – 104-common x 132-segment BIT MAP LCD DRIVER

NJU6678
(b)Voltage Adjust Circuits
The boosted voltage of VOUT output from V5 through the voltage adjust circuits for LCD driving. The output
voltage of V5 is adjusted by changing the Ra and Rb within the range of | V5 | < | VOUT |. The output voltage
is calculated by the following formula.
VLCD = VDD-V5 = (1+Rb/Ra)VREG (1)
VDD
Ra
R1
VREG
VR
V5
R2
R3
Rb
Fig. 3
The voltage of VREG is a standard voltage produced from built-in bleeder resistance. VREG is possible to be
fine-adjusted by EVR functions mentioned in (c).
For fine-adjustment of V5, R2 as variable resistor, R1 and R3 as fixed constant should be connected to VDD
terminal, VR and V5, as shown in Fig.3.
[ Design example for R1, R2 and R3 / Reference ]
- R1+R2+R3=5MΩ (Determined by the current flown between VDD-V5)
- Variable voltage range by the R2. -6V to -7.5V (VLCD=VDD-V5 --> 9.0V to 10.5V)
(Determined by the LCD electrical characteristics)
- VREG=3V(In case of EVR=(FF)H)
- R1, R2 and R3 are calculated by above conditions and the formula of (1) to below;
R1=2.0MΩ, R2=0.5MΩ, R3=2.5MΩ
* If the power supply voltage between VDD and VSS changes, V5 changes too. Therefore the power supply
voltage should be stabilized for V5 stable operation.