NJU6657 Datasheet, PDF (31/78 Pages) New Japan Radio – 88-common x 272-segment Bitmap LCD Driver

Confidential NJU6657
Preliminary
(1-24) OSCILLATION CIRCUIT
NJU6657 is equipped with the CR oscllation circuit, and generates internal clocks used for the display timing. The
generating method of the clock selects by the internal oscillation or external clock. When the internal oscillation circuit is
used, Oscillator starts after input of the Internal Oscillator ON/OFF command input. (INTCK=“H”)
In addition, oscillation frequency can be selected by programming the “Internal oscillation frequency control” instruction
So that is possible to optimize the Display duty.
When CLS=”L”, oscillation stops, and display clock is input from the OSC1 terminal.
When external oscillation circuit is operating by setting CLS terminal gives priority more than the operation of the
internal oscillation circuit.
CLS Terminal
L
L
H
H
INTCK
0
1
0
1
Ext. Input Status
Available
Available (Priority)
Not available
Not available
Internal Oscillator
Inactive
Active
Inactive
Active
When external clock input, the divide value is reflection setting by “Interanal oscillation circuit frequency set”
instruction. The divide set is normally using select by the 1 divide (“SH1 to 0 = “00”)
When partial display function used, the divide value changing by divide set instruction.
When frame frequency changes by partial display etc by external clock used.
You shuld be changing external clock frequency and also possible to have you change or to change oscillating frequency
using a divide setup.
The set to each of frequency value is shown in below. ( also in case of External CLK operation.)
Selllect of frame frequency
Sellect of display line
Caluculate of frequency * refer P56
Fix to OSC frequency
(Fix to OS4 to OS0 and SH1 to SH0
register value.)
Caluculate of Boost clock frequency
Use to OS4 to OS0 register value.
"Refer to P.60"
End
OSC1
( Ext. CLK Input )
CR OSC
#PPTU
%JWJEF
%JWJEF
Boost CLK
OSC
Frequency
(I t CLK)
BLOCK DIAGRAM
Ver.2012-11-22
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