NJU3152 Datasheet, PDF (2/11 Pages) New Japan Radio – 4-BIT SINGLE CHIP OTP TINY CONTROLLER

NJU3152
s BLOCK DIAGRAM
STACK
TLUaddr PC
MUX
OTP ROM
1024 x 8 bit
IR
ID
CPU CORE
X-Reg Y-Reg
AC
X’-Reg Y’-Reg
ALU
RAM
32 x 4 bit
CPU
TIMING
GENERATOR
STANDBY
CONTROLLER
OSC
V_DD
V_SS
TEST
RESET
OSC1
OSC2
PORT_A
PORT_B
PORT_E
PORT_D
PORT_C
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