NJU6645 Datasheet, PDF (19/112 Pages) New Japan Radio – 16-CHARACTER 6-LINE LCD DRIVER with JAPANESE KANJI ROM

Preliminary _NJU6645
(1-4) Serial Interface
The serial interface is transmitted with 5-line. While the chip select is active (CSb=“L”), the SDA and SCL
are enabled. While the chip select is inactive (CSb=“H”), the SDA and SCL are disabled, and the internal shift
register and the internal counter are being initialized. The data is interpreted as writes or reads according to
the RS.
8-bit serial data on the SDA is latched at the rising edge of the SCL signal in order of D7, D6,…, and D0, and
converted into 8-bit parallel data at the timing of the internal signal produced from the 8th SCL signal. The
data on the SDA is interpreted as display data or instruction according to the RS.
When the CSb signal is “H”, the interface is reset. The data of 1-character is processed by writing 2-byte. In
the DDRAM data writing, CSb is required to change to “H” once every 2-bytes. Because, it is recognized as
1-byte after CSb is changed from “H” to “L”.
Note that the SCL should be set to “L” right after data transmission or during non-access because the serial
interface is susceptible to external noises which may cause malfunctions.
In the read mode, selected address RAM data is read out after 1-dummy as for parallel interface. When the
RS and RW switches, it should be CSb="H".
Ver.2009-05-20
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