NJU6624C Datasheet, PDF (16/27 Pages) New Japan Radio – 14-CHARACTER 1-LINE DOT MATRIX LCD CONTROLLER DRIVER with SMOOTH SCROLL FUNCTION

NJU6624C
(j)Set Display Mode
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Code 1 0 0 0 1 1 1 0 * * * * * * K PD
The Set Display Mode instruction control the function of key scan and power down mode.
K
Function
1 Key scan ON
Key scan OFF
0 In busy of keyscan (tKS), all of segment terminal (S0 to S7) output the voltage
of V2.or VLCD2
PD
Function
1
Power down mode. All of common and segment terminal set the voltage level
of VLCD2
0 Release the power down mode.
In busy of Power down mode, do not input any instructions except for release the power down mode.
The power down mode should be set before power off because any irregular display appearance at power off is
prevented.
The key scan operation when switching to the power down mode during key scan.
When switching to the power down mode during key scan operation, it stops key scan operation
in the period and after power down mode cancellation too.
After power down mode cancellation, the REQ signal maintains "H" when detects key-in signal
before switches to power down mode and REQ signal rises to"H".
However, the key scan operation becomes invalid data even if it reads key-in data because
it stoppd.The key data becomes to valid with the key scan by the next key scan of frame.
(k)Set DD/MK RAM Address
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Code 1 0 0 1 0 0 1 1 * * * AD4 AD3 AD2 AD1 AD0
The address data (DB4 to DB0) is written into the address counter (AC) by this instruction.
After this instruction execution, the data writing is performed into the addressed DD/MK RAM.
The RAM includes DD RAM and MK RAM, and these RAMs are shared by address as shown below.
(l)Set CG RAM Address
DD RAM :
MK RAM :
RAM address
(00)H - (0D)H
(10)H - (1D)H
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Code 1 0 0 1 0 0 0 0 AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0
The CG RAM address set instruction is executed when the "H" level input to the AC terminal and the address is
written into DB7 to DB0 as shown above.
The address data (DB7 to DB0) is written into the address counter (AC) by this instruction.
After this instruction execution, the data writing is performed into the addressed RAM.
The RAM includes CG RAM address as shown below.
CG RAM :
RAM address
(00)H - (FE)H