NJU3427 Datasheet, PDF (16/18 Pages) New Japan Radio – 36 Outputs VFD Controller/Driver

NJU3427
Preliminary
• DC Characteristics 2
(VDD=3.0V, VSS=0V, Ta=-40 ~ 85°C)
Parameter
Symbol
Conditions
MIN TYP MAX Unit
Power Supply (1)
Power Supply (2)
H Level Input Voltage
L Level Input Voltage
Input off-leak current
Display Current
Pull-up Resistance
Pull-down Resistance
Logic Circuit
Power Supply
V_DD
V_FDP
V_IH
V_IL
I_IZ
I_OH
R_UR
R_DST
I_SS
V_DD pin
2.7
-
3.6
V
V_FDP pin and V_DD as reference
-40
-
V_SS
V
XT, RSTb, CSb, SCK, SI pins
0.8V_DD
-
-
-
-
0.2V_DD
V
CSb, SCK, SI pins
V_DD=3.6V, V_I=0 or 3.6V
-
-
±1
µA
DR₀ pin
V_DD=2.7V,V_FDP=V_DD-40 -5.0
-9.0
-
mA
DR₁ ~ DR₃₅ pin V, V_OH=V_DD-1.35V
-2.5 -4.0
-
mA
RSTb pin, Ta=25°C, V_I=V_SS
100
-
300 kΩ
DR₀ ~ DR₃₅ pins, Ta=25°C
V_I=V_DD, V_FDP=V_DD-40V
75
-
195 kΩ
V_SS pin
CR oscillation (R=4.7kΩ, C=100pF),
All Segment/Timing pins open, RSTb
open
-
0.25 0.35 mA
All Segment/Timing pins output display
OFF signal.
Operation Current
V_FDP pin, V_FDP=V_DD-40V,
I_FDP
CR oscillation (R=4.7kΩ, C=100pF),
-
All driving pins output display ON signal
12 16.5 mA
CR Oscillation Frequency
f_CR
Ta=25°C
R=4.7kΩ, C=100pF
1.05 1.13 1.21 MHz
• AC Characteristics 2
Parameter
External Clock Frequency
Width of External Clock Pulse
Data Setup Time
Data Hold Time
Clock Frequency
Clock Pulse Width
External Clock
Rising Time,
Falling Time
Clock Interval Time
Reset Pulse Width
Symbol
f_CL
t_CLH, t_CLL
t_SIS
t_SIH
f_SCK
t_SCKH, t_SCKL
t_CLH, t_CLL
t_SCI
t_RSTb
Conditions
Fig 1
Fig 1
Fig2
Fig2
Fig3
Fig3
Fig2
Fig3
Fig4
(VDD=3.0V, VSS=0V, Ta=-40 ~ 85°C)
MIN TYP MAX Unit
0.8
-
2.5 MH_Z
200
ns
35
ns
35
ns
2.0 MH_Z
200
ns
250 ns
10
µs
10
µs
- 16 -
Ver.2008-08-07