PCIE-7360 Datasheet, PDF (1/2 Pages) NIC-Components Corp. – 100 MHz 32-CH High-Speed Digital I/O Card

PCIe-7360
100 MHz 32-CH High-Speed Digital I/O Card
Features
˙ x4 lane PCI Express^® Interface
˙ 8/16/24/32-CH at up to100MHz for DI or DO
˙ 8/16-CH at up to 200MHz for DI in external clock mode
˙ 400 MB/s maximum throughput
˙ Voltage level software selectable from 1.8 V, 2.5 V, and
3.3 V
˙ 80-step phase shift in external clock mode
˙ Per group (8-bit) input/output direction selectable
˙ Support for I2C and SPI programmable serial interfaces
for external device communication
˙ Scatter-gather DMA support
˙ Flexible handshake and external digital trigger modes
˙ 8-channel auxiliary programmable I/O
Introduction
ADLINK’s PCIe-7360 is a high-speed digital I/O board with 32-CH bi-directional parallel I/O, with data rates up to 400
MB/s are available through the x4 PCI Express^® interface, and clock rates up to 100 MHz internal or 200 MHz external,
ideally suiting high speed and large scale digital data acquisition or exchange applications, such as digital image capture,
video playback and IC testing.
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I/O Port Configuration & Level Shifting
Initial power-up status for the onboard 32-channel I/O lines is as input lines. The 32-channel I/O lines are bi-directional and can
be divided into four groups, each carrying 8 channels and individually configurable as an input or output port. The PCIe-7360
also supports software selectable logic levels of 1.8 V, 2.5 V, and 3.3 V, with all four groups matching the chosen logic level. In
digital output mode, the outputs are tri-stated when the digital output lines are disabled. The programmable I/O direction and
logic levels provide a flexible interface for devices under test (DUT).
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Maximum Data Transfer Rate
The PCIe-7360 can support up to 400 MB/s throughput along with 32-bit data width at a maximum 100 MHz internal
clock rate or 8/16-bit data width at a maximum 200 MHz external clock rate. The combination scatter-gather bus-mas-
tering DMA, deep onboard 8 k-sample FIFO size, and x4 PCI Express^® interface guarantee no data loss during sustained
high-speed data processing.
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Phase Delay
The PCIe-7360 features phase shifting of external sample clock
or internal sample clock export, optimizing acquisition/generation
timing in high-speed data transfer applications. The phase shifting
of sample clock supports adjustment up to 80 steps, that is phase
shifting from 4.5° to 355.5°, preventing erroneous sampling during
transition states, such that sample timing is valid and stable.
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1²C & SPI Serial Interfaces
PCIe-7360’s application function I/O (AFI) can be configured as a I2C or
SPI master node. The I2C interface supports fast mode and uses two
bi-directional lines, SCL (serial clock) and SDA (serial data) respectively.
The SPI interface uses four-wire signaling based on SCK (serial clock), SI (serial data input), SO (serial data output), and CS (chip
select). Peripheral devices can communicate directly via the PCIe-7360’s built-in I2C or SPI protocols along with provided APIs.
Software Support
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OS Information

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Windows XP, Windows 7/8 x64/x86, Linux
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Software Compatibility

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LabVIEW, MATLAB, Visual Studio.NET
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PCIe-7360 Block Diagram