PXI-6541 Datasheet, PDF (2/3 Pages) National Instruments Corporation – 100 and 50 MHz Digital Waveform Generator/Analyzers

100 and 50 MHz Digital Waveform
Generator/Analyzers
Specifications
For detailed specifications, please visit ni.com/info and enter: pxi6541, pxi6542.
These specifications are valid for the following temperature ranges: PXI: 0 to 55 °C.
Channel Characteristics
Number of data channels................................. 32
Direction control of data channels .................. Per channel
Generation Signal Characteristics (data, DDC ClkOut, and PFI <0:3> channels)
All voltage ranges specified into 1 MΩ
Generation voltage families (V) ....................... 1.8, 2.5, 3.3 logic families (5 V compatible)
Generation signal type..................................... Single-ended
Generation voltage levels
Family
Settings (V)
1.8
2.5
3.3
5.0
Low Voltage Levels (V)
Typical
Max
0
0.1
0
0.1
0
0.1
0
0.1
High Voltage Levels (V)
Min
Typical
1.7
1.8
2.4
2.5
3.2
3.3
3.2
3.3
I=100 µA
Output impedance ............................................ 50 Ω nominal at 25 °C
Maximum DC drive strength ............................ ±8 mA at 1.8 V
±16 mA at 2.5 V
±32 mA at 3.3 V
Channel power-up state................................... Drivers disabled, 10 kΩ input impedance
Acquisition Signal Characteristics (data, strobe, and PFI <0:3> channels)
Acquisition voltage families (V) ....................... 1.8, 2.5, 3.3, 5.0 logic families
Acquisition voltage levels
Family
Settings (V)
1.8
2.5
3.3
5.0
Low Voltage Thresholds (V)
Max
0.45
0.75
1.0
1.0
High Voltage Thresholds (V)
Min
1.35
1.75
2.3
2.3
Input impedance............................................... High impedance (10 kΩ)
Timing Characteristics
Sample Clock
Sample clock sources....................................... 1. Onboard clock (internal VCXO with divider)
2. CLK IN (SMB)
3. PXI_STAR (PXI only)
4. STROBE (DDC Connector) – Acquisition only
On board clock frequency range ..................... NI 6541: 48 Hz to 50 MHz.
(Settable to 200 MHz / N; 4 ≤ N ≤ 4,194,304)
NI 6542: 48 Hz to 100 MHz.
(Settable to 200 MHz / N; 2 ≤ N ≤ 4,194,304)
Exported sample clock delay range ................. 0 - 1 sample clock periods for clock frequencies ≥ 25 MHz
Exported sample clock delay resolution .......... 1/256 of sample clock period for clock frequencies ≥ 25 MHz
Exported sample clock jitter (typical using onboard clock)
Period jitter
20 ps (rms)
Cycle-to-cycle jitter
35 ps (rms)
Generation Signal Characteristics (data, DDC Clk Out, and PFI <0:3> channels)
Data channel-to-channel skew ........................ ±600 ps (typical across all data channels)
Maximum data channel toggle rate ................ NI 6541: 25 MHz; NI 6542: 50 MHz
Data position modes ........................................ Rising edge, falling edge, delayed relative to sample clock
Generation data delay range ........................... 0 - 1 sample clock period for clock frequencies ≥ 25 MHz
Generation data delay resolution .................... 1/256 of sample clock period for clock frequencies ≥ 25 MHz
Acquisition Signal Characteristics (data, strobe, and PFI <0:3> channels)
Channel-to-channel skew ................................ ±600 ps (typical across all data channels)
Acquisition timing delay range ........................ 0 - 1 sample clock periods for clock frequencies ≥ 25 MHz
Acquisition timing delay resolution ................. 1/256 of sample clock period for clock frequencies ≥ 25 MHz
Waveform Characteristics
Memory and Scripting
Onboard memory size
1 Mb/channel
8 Mb/channel
64 Mb/channel
(assumes no scripting (for generation sessions) (for generation sessions) (for generation sessions)
instructions)
1 Mb/channel
8 Mb/channel
64 Mb/channel
(for acquisition sessions) (for acquisition sessions) (for acquisition sessions)
Generation modes
Waveform: Generate a single waveform once, N times, or continuously.
Scripted: Generate a simple or complex sequence of waveforms. Use scripts to describe the waveforms
to be generated, the order in which the waveforms are generated, how many times the waveforms are
generated, and how the device responds to script triggers.
Triggers (inputs to the NI 654x)
Trigger types..................................................... Start Trigger, Pause Trigger, Script Trigger <0:3>
(Generation sessions only), Reference Trigger
(Acquisition sessions only)
Sources ............................................................ 1. PFI <0> (SMB Jack connectors)
2. PFI <1:3> (DDC connector)
3. PXI_TRIG<0:7> (PXI backplane, PXI only)
4. PXI STAR (PXI backplane, PXI only)
5. Pattern match (Acquisition sessions only)
6. Software (User function call)
7. Disabled (Do not wait for a trigger)
Trigger detection .............................................. 1. Start Trigger (Edge detection: rising or falling)
2. Pause Trigger (Level detection: high or low)
3. Script Trigger <0:3> (Edge detection: rising or falling,
Level detection: high or low)
4. Reference Triggers (Edge detection: rising or falling)
Minimum required trigger pulse width............ 40 ns
Destinations ..................................................... 1. PFI <0> (SMB Jack Connector)
2. PFI <1:3> (DDC Connector)
3. PXI_TRIG <0:7> (PXI Backplane)
Each of the Triggers can be routed to any of the 13
Destinations with the exception of Pause Trigger.
Pause Trigger can not be exported.
Events (outputs from the NI 654x)
Event types ....................................................... Marker, Data Active Event, Ready for Start Event
Destinations ..................................................... 1. PFI <0> (SMB Jack Connectors)
2. PFI <1:3> (DDC Connector)
3. PXI_TRIG <0:7> (PXI Backplane)
Each of the Events can be routed to any of the destinations
with the exception of Data Active Event. Data Active Event
can only be routed to the PFI channels.
Miscellaneous
Onboard Clock characteristics (Only valid when PLL Reference Source is set to None)
Frequency accuracy .......................................... ±100 ppm (typical)
Temperature stability ....................................... ±30 ppm (typical)
Aging ............................................................ ±5 ppm first year (typical)
Power Requirements
Typical ............................................................ 15 W
Maximum.......................................................... 20.5 W
Physical
Dimensions....................................................... PXI: Single 3U CompactPCI Slot. PXI Compatible
I/O Panel Connectors
Label
CLK IN
PFI 0
CLK OUT
Digital data and
Control (DDC)
External Function(s)
Sample Clock, External PLL
Reference Input
Events, Triggers
Exported Sample Clock,
Exported Reference Clock
Digital data channels, Exported
Sample Clock, STROBE, Events, Triggers
Connector Type
SMB jack
SMB jack
SMB jack
68 pin VHDCI
Environment
Operating temperature..................................... PXI: 0 to 55 °C in all NI PXI chassis except the following.
0 to 45 °C when installed in an NI PXI-1000/B and
PXI-101x chassis. (Meets IEC-60068-2-1 and IEC-60068-2-2)
Storage temperature ........................................ -20 to 70 °C
Relative humidity ............................................. 10 to 90% relative humidity, noncondensing
(meets IEC-60068-2-56)
Storage Relative humidity................................ 5 to 95% relative humidity, noncondensing
(meets IEC-60068-2-56)
Compliance
Safety
NI 654x devices meet the requirements of the following standards for safety and electrical equipment for
measurement, control, and laboratory use:
IEC 61010-1, EN 61010-1
UL 3111-1, UL 61010B-1
CAN/CSA C22.2 No. 1010.1
Note: For full EMC compliance, you must operate this device with shielded cabling. In addition, all covers and
filler panels must be installed. See the Declaration of Conformity (DoC) for this product for any additional
regulatory compliance information. To obtain the DoC for this product, visit ni.com/hardref.nsf
National Instruments • Tel: [phone] • Fax: [phone] • [e-mail] • ni.com 2