UPD75236 Datasheet, PDF (91/190 Pages) NEC – 4-BIT SINGLE-CHIP MICROCOMPUTER

Table 4-6 Various Types of Signals in SBI Mode (1/2)
Signal Name
Bus release
signal
(REL)
Output
Device
Master
Definition
Rising edge of SB0/SB1 when
SCK0 = 1
SCK0
SB0/SB1
Timing Chart
"H"
Output
Condition
• RELT set
Effect on
Flag
Meaning of
Signal
• RELD set ^{CMD signal is output to}
• CMDD clear ^{indicate that transmit}
data is an address.
Falling edge of SB0/SB1 when
SCK0 = 1
Command signal
(CMD)
Master
SCK0
"H"
SB0/SB1
Acknowledge
signal (ACK)
Busy signal
(BUSY)
Ready signal
(READY)
Master/
slave
Slave
Slave
Low–level signal to be output
to SB0/SB1 during one-clock
period of SCK0 after comple-
tion of serial reception
[Synchronous Busy Output]
[Synchronous busy signal]
Low–level signal to be output
to SB0/SB1 following the
acknowledge signal
SCK0
SB0/SB1 D0
9
ACK
BUSY
High- level signal to be output
to before serial transfer start ^{SB0/SB1 D0}
ACK BUSY
or after its compleltion
• CMDT set • CMDD set
Œ ACKE = 1 • ACKD set
 ACKT set
i) Transmit data is an
address after REL
signal output
ii) No REL signal output.
Transmit data is a
command.
Completion of reception
• BSYE = 1
—
READY
ΠBSYE = 0
—
READY _{ Execution of}
an instruc-
tion for data
write to
SIO0
(transfer
start
command)
Serial reception disabled
because of processing
Serial reception enabed