UPD4481162 Datasheet, PDF (9/28 Pages) NEC – 8M-BIT ZEROSB SRAM PIPELINED OPERATION

µPD4481162, 4481182, 4481322, 4481362
[µPD4481322, µPD4481362]
A0 to A17
MODE
CLK
K
/CKE
Address
register 0
18
16
18
A1
A1’
A0
A0’
Burst
ADV ^logic
K
Write address
register 1
Write address
register 0
18
18
ADV
/BW1
/BW2
/BW3
/BW4
/WE
Write registry and
data coherency
control logic
Write
drivers
Memory Cell Array
1,024 rows
256 x 32 columns
(8,388,608 bits)
256 x 36 columns
(9,437,184 bits)
32/36
Input
register
1^E
32/36
32/36
32/36
E
E
Input
register
0^E
I/O1 to I/O32
I/OP1 to I/OP4
32/36
/G
/CE
CE2
/CE2
ZZ
Read
logic
Power down control
[µPD4481322, µPD4481362]
Interleaved Burst Sequence Table (MODE = VDD)
External Address
1st Burst Address
2nd Burst Address
3rd Burst Address
A17 to A2, A1, A0
A17 to A2, A1, /A0
A17 to A2, /A1, A0
A17 to A2, /A1, /A0
Linear Burst Sequence Table (MODE = VSS)
External Address
1st Burst Address
2nd Burst Address
3rd Burst Address
A17 to A2, 0, 0
A17 to A2, 0, 1
A17 to A2, 1, 0
A17 to A2, 1, 1
A17 to A2, 0, 1
A17 to A2, 1, 0
A17 to A2, 1, 1
A17 to A2, 0, 0
A17 to A2, 1, 0
A17 to A2, 1, 1
A17 to A2, 0, 0
A17 to A2, 0, 1
A17 to A2, 1, 1
A17 to A2, 0, 0
A17 to A2, 0, 1
A17 to A2, 1, 0
Data Sheet M15562EJ3V0DS
9