UPD444008L Datasheet, PDF (9/16 Pages) NEC – 4M-BIT CMOS FAST SRAM 512K-WORD BY 8-BIT

µPD444008L
Write Cycle
Parameter
Symbol
-A8
MIN. MAX.
-A10
MIN. MAX.
-A12
MIN. MAX.
Unit Notes
Write cycle time
tWC
8
10
12
ns
/CS to end of write
tCW
6
7
8
ns
Address valid to end of write
tAW
6
7
8
ns
Write pulse width
tWP
6
7
8
ns
Data valid to end of write
tDW
4
5
6
ns
Data hold time
tDH
0
0
0
ns
Address setup time
tAS
0
0
0
ns
Write recovery time
tWR
0
0
0
ns
/WE to output in high impedance
tWHZ
4
5
6
ns 1, 2
Output active from end of write
tOW
3
3
3
ns
Notes 1. Transition is measured at ± 200 mV from steady-state voltage with the output load shown in Figure 2.
2. These parameters are periodically sampled and not 100% tested.
Write Cycle Timing Chart 1 (/WE Controlled)
tWC
Address (Input)
/CS (Input)
/WE (Input)
I/O (Input / Output)
tCW
tAW
tAS
tWP
tWR
tWHZ
Indefinite data out
High
impe-
dance
tOW
tDW
tDH
Data in
High
impe-
dance
Indefinite data out
Cautions 1. /CS or /WE should be fixed to high level during address transition.
2. Do not input data to the I/O pins while they are in the output state.
Remarks 1. Write operation is done during the overlap time of a low level /CS and a low level /WE.
2. When /WE is at low level, the I/O pins are always high impedance. When /WE is at high level, read
operation is executed. Therefore /OE should be at high level to make the I/O pins high impedance.
Data Sheet M14429EJ4V0DS
9