UPD75518 Datasheet, PDF (88/180 Pages) NEC – 4 BIT SINGLE-CHIP MICROCOMPUTER

µPD75518(A)
Fig. 4-35 Format of Serial Operation Mode Register 0 (CSIM0) (3/3)
Signal from address comparator (R)
COI^Note
Condition for being cleared (COI = 0)
When the slave address register (SVA) does not match
the data of the shift register
Condition for being set (COI = 1)
When the slave address register (SVA) matches the
data of the shift register
Note COI can be read only before serial transfer is started or after serial transfer is completed. An
undefined value may be read during transfer.
COI data written by an 8-bit manipulation instruction is ignored.
Serial interface operation enable/disable specification bit (W)
CSIE0
Shift register operation
Serial clock counter
IRQCSI0 flag
0
Shift operation disabled
Cleared
Held
1
Shift operation enabled
Count operation
Can be set.
SO0/SB0, SI0/SB1 pin
Used only for port 0
Used in each mode as
well as for port 0
Remarks 1. Each mode can be selected by setting CSIE0, CSIM03, and CSIM02.
CSIE0
0
1
1
1
CSIM03
×
0
1
1
CSIM02
×
×
0
1
Operation mode
Operation halt mode
Three-wire serial I/O mode
SBI mode
Two-wire serial I/O mode
2. The P01/SCK0 pin assumes the following state according to the setting of CSIE0, CSIM01, and
CSIM00:
CSIE0
0
1
0
0
0
1
1
1
CSIM01
0
0
1
0
1
1
0
1
CSIM00
0
0
0
1
1
0
1
1
P01/SCK0 pin state
Input port
High impedance
High level output
Serial clock output (High level output)
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