UPD16602 Datasheet, PDF (8/16 Pages) NEC – 312-OUTPUT TFT-LCD FULL COLOR DRIVER

µPD16602
(3) Sampling and hold timing (R/L = “L”)
S/D = “L” (Dual Bank Arrangement)
Line (N – 1) writing
HS
PL/NL^Note
(S/H)P
Line (N – 1)
output
(S/H)N
Line N
sampling
Line N writing
Line (N + 1)
sampling
Line N
output
Line (N + 1) writing
Line (N + 1)
output
Line (N + 2)
sampling
S1 to S312
Positive output
Line (N – 1)
Line N
Negative output
Positive output
Line (N + 1)
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Note PL/NL = H; input negative analog display signal.
PL/NL = L; input positive analog display signal.
S/D = “H” (Single Bank Arrangement)
Line (N – 1) writing
HS
PL/NL^Note
Line N writing
(S/H)P of Add pin
(S/H)N of Add pin
Line (N – 1)
output
Line N
sampling
Line (N + 1)
sampling
Line N
output
(S/H)P of Even pin
(S/H)N of Even pin
Line N
sampling
Line (N – 1)
output
Line N
output
Line (N + 1)
sampling
Line (N + 1) writing
Line (N + 1)
output
Line (N + 2)
sampling
Line (N + 2)
sampling
Line (N + 1)
output
S2n + 1 (Add pin)
S2n (Even pin)
Positive output
Line (N – 1)
Line N
Negative output
Positive output
Line (N + 1)
Line (N – 1)
Negative output
Positive output
Line N
Line (N + 1)
Negative output
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Note Odd number pin
Even number pin
PL/NL = H; input negative analog display signal.
PL/NL = L; input positive analog display signal.
PL/NL = H; input positive analog display signal.
PL/NL = L; input negative analog display signal.
8