MC-458CA726 Datasheet, PDF (8/16 Pages) NEC – 8M-WORD BY 72-BIT SYNCHRONOUS DYNAMIC RAM MODULE UNBUFFERED TYPE

MC-458CA726
Synchronous Characteristics
Parameter
Clock cycle time
/CAS latency = 3
/CAS latency = 2
Access time from CLK
/CAS latency = 3
/CAS latency = 2
CLK high level width
CLK low level width
Data-out hold time
Data-out low-impedance time
Data-out high-impedance time /CAS latency = 3
/CAS latency = 2
Data-in setup time
Data-in hold time
Address setup time
Address hold time
CKE setup time
CKE hold time
CKE setup time (Power down exit)
Command (/CS0, /CS2, /RAS, /CAS, /WE,
DQMB0 - DQMB7) setup time
Command (/CS0, /CS2, /RAS, /CAS, /WE,
DQMB0 - DQMB7) hold time
Note 1. Output load
Output
Symbol
tCK3
tCK2
tAC3
tAC2
tCH
tCL
tOH
tLZ
tHZ3
tHZ2
tDS
tDH
tAS
tAH
tCKS
tCKH
tCKSP
tCMS
-A 80
MIN.
MAX.
8
(125 MHz)
10 (100 MHz)
6
6
3
3
3
0
3
6
3
6
2
1
2
1
2
1
2
2
-A 10
Unit
MIN.
MAX.
10
(100 MHz) ^ns
13
(77 MHz) ^ns
6
ns
7
ns
3
ns
3
ns
3
ns
0
ns
3
6
ns
3
7
ns
2
ns
1
ns
2
ns
1
ns
2
ns
1
ns
2
ns
2
ns
tCMH
1
1
ns
Z = 50 Ω
50 pF
Note
1
1
1
Remark These specifications are applied to the monolithic device.
8
Data Sheet M13050EJ7V0DS00