UPD70208H Datasheet, PDF (70/110 Pages) NEC – V40HLTM, V50HLTM 16/8, 16-BIT MICROPROCESSOR

µPD70208H, 70216H
(1) µPD70208H, 70216H-10/12/16 (TA = –40 to +85 °C, VDD = 5 V ±10%) (3/3)
Output Pin Load Capacitance: CL = 100 pF
Parameter
RXD hold time (vs. SCU internal clock↓)
CLKOUT↓ → SRDY delay time
TOUT1↓ → TXD delay time
TCTL2 setup time (vs. CLKOUT↓)
TCTL2 setup time (vs. TCLK↑)
TCTL2 hold time (vs. CLKOUT↓)
TCTL2 hold time (vs. TCLK↑)
TCTL2 high-level width
TCTL2 low-level width
TOUT output delay time (vs. CLKOUT↓)
TOUT output delay time (vs. TCLK↓)
TOUT output delay time (vs. TCTL2↓)
TCLK rise time
TCLK fall time
TCLK high-level width
TCLK low-level width
TCLK cycle
Access interval^{Note 1}
REFRQ↑ delay time (vs. MRD↑)^{Note 2}
RESET pulse width^{Note 3}
Symbol
µPD70208H-10 µPD70208H-12
µPD70216H-10 µPD70216H-12
µPD70208H-16
µPD70216H-16 ^Unit
MIN. MAX. MIN. MAX. MIN. MAX.
<69> tHRX
500
500
500
ns
<70> tDKSR
100
100
100 ns
<71> tDTX
200
200
200 ns
<72> tSGK
40
40
40
ns
<73> tSGTK
40
40
40
ns
<74> tHKG
80
80
80
ns
<75> tHTKG
40
40
40
ns
<76> tGGH
40
40
40
ns
<77> tGGL
40
40
40
ns
<78> tDKTO
150
150
150 ns
<79> tDTKTO
100
100
100 ns
<80> tDGTO
90
90
90 ns
<81> tTKR
25
25
25 ns
<82> tTKF
25
25
25 ns
<83> tTKTKH
45
40
30
ns
<84> tTKTKL
45
40
30
ns
<85> tCYTK
100
DC
80
DC
62.5
DC ns
<86> tAI
2tCYK–40
2tCYK–25
2tCYK–20
ns
<87> tDRQHRH tKKL–30
tKKL–15
tKKL–10
ns
<88> tWRESL
4tCYK
4tCYK
4tCYK
ns
Notes 1. Specification to guarantee read/write recovery time for I/O device.
2. Specification to guarantee that REFRQ↑ is always later than MRD↑.
Only guaranteed when the EREF bit of the SCTL register is 0.
3. When using internal clock generator by connecting a resonator to the X1 and X2 pins, the oscillation
stabilization time must be added at power-ON. Because the oscillation stabilization time varies depending
on the characteristics of the resonator and oscillator used, evaluate the oscillation stabilization time with the
resonator and oscillator actually used.
70
Data Sheet U13225EJ4V0DS00