UPD63310 Datasheet, PDF (7/28 Pages) NEC – STEREO SOUND CODEC

µPD63310
1. DESCRIPTION OF OPERATIONS
1.1 Analog Input Block
The analog input block enables signal input from two channels. Four different stereo signals (IN1 to IN4) and a
monaural signal (IN5) can be mixed and input via these channels. The volume can be adjusted for each analog signal,
and the sum of the volume settings is input to the ADC. A 6-bit signal is used to adjust the volume within an adjustment
range (in 1.5-dB steps) from –46.5 dB to 0 dB, plus a mute setting. A low-noise mic amp (variable gain width: 10 to 30
dB) is provided on-chip for mic input.
1.2 Analog Output Block
The analog output block enables signal output from two channels. Five different analog signals (IN1 to IN4 and DAC)
can be mixed and output via these channels. The volume can be adjusted for each analog signal, and the sum of the
volume settings is output (via OUTL and OUTR pins). A 6-bit signal is used to adjust the volume within an adjustment
range (in 1.5-dB steps) from –46.5 dB to 0 dB, plus a mute setting. The output from the DAC (via DACL and DACR pins)
can be monitored directly.
1.3 Digital Interface
A serial interface for audio is supported for input and output of digital audio data (two’s complement, MSB first).
BCLK and LRCLK are automatically generated on chip from the master clock that is supplied to MCLK pin from an
external source. BCLK and LRCLK are used by the ADC and DAC. In other words, the ADC’s and DAC’s sampling
frequency is determined based on the master clock and cannot be set independently of it.
A parallel interface is used for input and output of the 6-bit data used for volume adjustments. The target registers for
parallel data I/O are selected via the SELR pin. This pin selects an address register when at low level and a data register
when at high level.
OEB is output as the bus driver’s enable signal and RBW is output as the bus driver’s direction specification signal.
Use this pin as necessary. If it is not used, leave it unconnected.
When the clock (data) input to the MCLK and SI pins has been stopped, set these pins to either high level or low level
(if necessary, connect via a resistance to DVDD or DGND).
(1) Serial interface
BCLK
LRCLK
SI, SO
L-channel data
R-channel data
15 14 13 12
4 3 2 1 0 15 14 13 12
43210
LSB
LSB
(2) Parallel interface
CSB (I)
RB (I)
WB (I)
OEB (O)
RBW (O)
DATA5- (I/O)
DATA0
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