UPD754302 Datasheet, PDF (59/74 Pages) NEC – 4-BIT SINGLE-CHIP MICROCONTROLLER

Interrupt Input Timing
INT0,1,2,4
KR0-7
µPD754302, 754304, 754302(A), 754304(A)
tINTL
tINTH
RESET Input Timing
tRSL
RESET
Data Memory STOP Mode Low-Supply Voltage Data Retention Characteristics (TA = –40 to +85 °C)
Parameter
Symbol
Test Conditions
Release signal set time tSREL
Oscillation stabilization tWAIT
Release by RESET
wait time ^Note1
Release by interrupt request
MIN. TYP. MAX. Unit
0
µs
Note2
ms
Note3
ms
Notes 1.
2.
3.
The oscillation stabilization wait time is the time during which the CPU operation is stopped to
avoid unstable operation at oscillation start.
2¹⁷/fx and 2¹⁵/fx can be selected with mask option.
Depends on setting of basic interval timer mode register (BTM) (see table below).
BTM3
–
–
–
–
BTM2
0
0
1
1
BTM1
0
1
0
1
BTM0
0
1
1
1
Wait Time
When fX = 4.19 MHz
When fX = 6.0 MHz
2²⁰/fX (Approx. 250 ms)
2²⁰/fX (Approx. 175 ms)
2¹⁷/fX (Approx. 31.3 ms)
2¹⁷/fX (Approx. 21.8 ms)
2¹⁵/fX (Approx. 7.81 ms)
2¹⁵/fX (Approx. 5.46 ms)
2¹³/fX (Approx. 1.95 ms)
2¹³/fX (Approx. 1.37 ms)
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