UPD30121 Datasheet, PDF (58/76 Pages) NEC – VR4121TM 64-/32-BIT MICROPROCESSOR

µPD30121
(15) High-speed system bus parameter (ZWS#) (1/2)
Parameter
Address setup time (to command signal ↓)^{Notes 1, 2}
Command signal low-level width^{Notes 1, 2}
Address hold time (from command signal ↑)^{Note 1}
Command signal recovery time^{Notes 1, 2}
ZWS# ↓ delay time from command signal ↓^{Notes 1, 2}
ZWS# signal hold time (from command signal ↑)^{Note 1}
Data output setup time (to command signal ↓)^{Note 1}
Data output hold time (from command signal ↑)^{Note 1}
MEMCS16#/IOCS16# sampling start time^{Note 2}
Symbol
tAVCL
tCLCH
tCHAV
tCHCL
tCLZL
tCHZH
tDVCL
tCHDV
tAVSV2
MEMCS16#/IOCS16# hold time (from command
signal ↑)^{Note 1}
Data input setup time
Data input hold time
tCHSV
tDS
tDH
Condition
MIN.
MAX.
Unit
T × N − 29
ns
T × N − 19
ns
25
ns
T × (N + 1) − 29
ns
T × (N − 1) − 20 ns
0
ns
−15
ns
25
ns
2 × T × (N – 1)
ns
– 44
0
ns
0
ns
5
ns
Notes 1. With the VR4121, the MEMW# and MEMR# signals are called the command signals for the high-speed
system bus interface.
2. The value of N is set by using the WISAA (0:2) bits of the BCUSPEEDREG register.
The value of T is set by using the CLKSEL (0:2) signals (TxD/CLKSEL2, RTS#/CLKSEL1, and
DTR#/CLKSEL0 pins).
CLKSEL2
Signal
1
1
1
1
0
0
0
0
CLKSEL1
Signal
1
1
0
0
1
1
0
0
CLKSEL0
Signal
1
0
1
0
1
0
1
0
T (ns)
RFU
35
33
30
33
30
33
38
WISAA2 Bit WISAA1 Bit WISAA0 Bit
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
N
(TClock)
8
7
6
5
4
3
2
1
Remarks 1. Do not set CLKSEL (2:0) signal
= 111.
2. Do not set CLKSEL (2:0) signal
= 110, 101 with 131 MHz model.
58
Data Sheet U14691EJ1V0DS00