UPD75304B Datasheet, PDF (55/76 Pages) NEC – 4-BIT SINGLE-CHIP MICROCOMPUTER

µPD75304B,75306B,75308B
DC CHARACTERISTICS (Ta = –40 to +85 °C, VDD = 2.0 to 6.0 V) (2/2)
PARAMETER
SYMBOL
TEST CONDITIONS
On-chip pull-up
resistor
Ports 0, 1, 2, 3, 6
RL1
and 7 (Except P00) VDD = 2.5 V ±10%
VIN = 0 V
Ports 4 and 5
RL2
VOUT = VDD –1.0 V
VDD = 2.5 V ±10%
LCD drive voltage
VLCD
LCD split resistor
RLCD
LCD output voltage
deviation *1
(common)
LCD output
voltage deviation
(segment)
VODC
VODS
IO = ±5 µA
IO = ±1 µA
VLCDO = VLCD
VLCD1 = VLCD × 2/3
VLCD2 = VLCD × 1/3
2.0 V ≤ VLCD ≤ VDD
VDD = 3 V ±10%*4
IDDI
4.19 MHz*3
crystal oscillation ^{VDD = 2.5 V ±10%*4}
C1 = C2 = 22 pF
low-speed mode
HALT VDD = 3 V ±10%
IDD2
mode VDD = 2.5 V ±10%
Supply current*2
VDD = 3 V ±10%
IDD3
32 kHz*5
VDD = 2.5 V ±10%
crystal oscillation _{HALT VDD = 3 V ±10%}
IDD4
mode VDD = 2.5 V ±10%
MIN.
50
10
2.0
60
0
0
IDD5
XT1 = 0 V
STOP mode
VDD = 3 V ±10%
Ta = 25 °C
VDD = 2.5 V
±10%
Ta = 25°C
TYP.
MAX.
UNIT
600
kΩ
60
kΩ
VDD
V
100
150
kΩ
±0.2
V
±0.2
V
0.4
1.2
mA
0.3
0.9
mA
180
540
µA
120
360
µA
40
120
µA
25
75
µA
12
36
µA
9
27
µA
0.5
15
µA
0.5
5
µA
0.4
15
µA
0.4
5
µA
* 1. The voltage deviation is the difference between the output voltage and the segment or common output
desired value (VLCDn; n = 0, 1, 2).
2. Current which flows in the on-chip pull-up resistor or LCD split resistor is not included.
3. Including oscillation of the subsystem clock.
4. When PCC is set to 0000 and the device is operated in the low-speed mode.
5. When the system clock control register (SCC) is set to 1001 and the device is operated on the subsystem
clock, with main system clock oscillation stopped.
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