UPD30181A Datasheet, PDF (52/72 Pages) NEC – 64-/32-BIT MICROPROCESSOR

µPD30181A, 30181AY
(d) External ISA bus space access (READY mode) timing (RDYSYN = 1)
IOCS16SET CONSET RMINWID CONOFF CSOFF
+tEXD
+tEXD
+tEXD
+tEXD
+tEXD
BUSIDLE
+tEXD
A(24:0), UBE#
(output)
IORD#, IOWR#,
MEMRD#, MEMWR#
(output)
tEXD
SYSEN#
(output)
tEXD
tEXD
SYSDIR
(output)
tTClock
+tEXD
D(15:0)
(read)
Note
tEXZ
D(15:0)
(write)
Hi-Z
tEXD
Hi-Z
Input
tTClock
+tEXD
Note
Hi-Z
tEXS tEXH
tEXD
tEXCL
IORDY
(input)
IOCS16#
(input)
2tTClock+tLClock+tEXD
tEXRDYH
tLClock+tEXD
tEXCS16H
Note Output
Remarks 1. IOCS16SET, CONSET, CSOFF, RMINWID, CONOFF, and BUSIDLE are the timing parameters
that can be changed by setting registers of the EXIBU. Each timing parameter is defined as the
number of LClock cycles.
2. The circles indicate the sampling timing.
52
Data Sheet U16277EJ1V0DS