UPD753036 Datasheet, PDF (51/88 Pages) NEC – 4-BIT SINGLE-CHIP MICROCONTROLLER

µPD753036, 753036(A)
Instruction
Mnemonic
Group
Operand
Branch
BR^Note1
addr
addr1
!addr
$addr
$addr1
PCDE
PCXA
BCDE^{Note 2}
BCXA^{Note 2}
BRA^{Note 1} !addr1
BRCB
!caddr
Subroutine CALLA^{Note 1} !addr1
stack control
CALL^{Note 1} !addr
CALLF^{Note 1} !faddr
Number ^Number
of Machine
of Bytes _Cycles
Operation
–
–
PC13–0 ← addr
Select appropriate instruction from
among BR !addr, BRCB !caddr, and
BR $addr according to the assembler
being used.
BR !addr
BRCB !caddr
BR $addr
–
–
PC13–0 ← addr1
Select appropriate instruction from
the following according to the
assembler being used.
BR !addr
BRA !addr1
BRCB !caddr
BR $sddr1
3
3
PC13–0 ← addr
1
2
PC13–0 ← addr
1
2
PC13–0 ← addr1
2
3
PC13–0 ← PC13–8+DE
2
3
PC13–0 ← PC13–8+XA
2
3
PC13–0 ← B1,0+CDE
2
3
PC13–0 ← B1,0+CXA
3
3
PC13–0 ← addr1
2
2
PC13–0 ← PC13,12+caddr11-0
Addressing
Skip Condition
Area
*6
*11
*6
*7
*6
*6
*11
*8
3
3
(SP–5)(SP–6)(SP–3)(SP–4) ← 0, 0, PC13–0
*11
(SP–2) ← ×, ×, MBE, RBE
PC13–0 ← addr1, SP ← SP–6
3
3
(SP–4)(SP–1)(SP–2) ← PC11–0
*6
(SP–3) ← MBE, RBE, PC13, PC12
PC13–0 ← addr, SP ← SP–4
4
(SP–5)(SP–6)(SP–3)(SP–4) ← 0, 0, PC13–0
(SP–2) ← ×, ×, MBE, RBE
PC13–0 ← addr, SP ← SP–6
2
2
(SP–4)(SP–1)(SP–2) ← PC11–0
*9
(SP–3) ← MBE, RBE, PC13, PC12
PC13–0 ← 000+faddr, SP ← SP–4
3
(SP–5)(SP–6)(SP–3)(SP–4) ← 0, 0, PC13–0
(SP–2) ← ×, ×, MBE, RBE
PC13–0 ← 000+faddr, SP ← SP–6
Notes 1.
2.
The above operations in the shaded boxes can be performed only in the Mk II mode. The other
operations can be performed only in the Mk I mode.
Only the low-order 2 bits are valid for the B register.
Data Sheet U11353EJ4V0DS00
51