UPD2845GR Datasheet, PDF (5/16 Pages) NEC – 1 V, 1.3 mA, 94MHz PLL SYNTHESIZER LSI FOR PAGER SYSTEM

P_PD2845GR
ELECTRICAL CHARACTERISTICS
DC PERFORMANCE (Unless otherwise specified, VDD1 = 1.00 V to 1.15 V, VDD2 = 2.70 to 3.30 V, TA = ð10 to +50 °C)
PARAMETER
Supply Voltage
Circuit Current
SYMBOL
VDD1
VDD2
IDD1
MIN.
1.00
2.70
Data Retain Current
IDR
High Level Output Current1^*1
IOH1
ð1.0
High Level Output Current2^*1
IOH2
High Level Output Current3^*1
IOH3
Low Level Output Current1^*2
IOL1
ð0.5
ð0.1
1.0
Low Level Output Current2^*2
IOL2
Low Level Output Current3^*2
IOL3
High Level Input Current1^*2
IIH1
Low Level Input Current1^*1
IIL1
High Level Input Current2^*2
IIH2
0.4
0.4
0.4
ð0.4
High Level Input Voltage1
VIH1
0.8 u VDD1
Low Level Input Voltage1
VIL1
0
High Level Input Voltage2
VIH2
0.8 u VDD1
Low Level Input Voltage2
VIL2
0
Output Leak Current
IL
*1 Current from IC
*2 Current into IC
TYP.
1.05
3.0
1.3
1.0
10^ð4
MAX.
1.15
3.30
2.2
10
1.0
4.0
0.2 u VDD1
VDD1
0.2 u VDD1
r1.0
UNIT
V
V
mA
PA
mA
mA
mA
mA
mA
mA
PA
PA
PA
V
V
V
V
PA
CONDITIONS
PLL Operation
P/D Charge pump block
fin = 70 MHz, 0.2 VP-P.
fx’tal = 12.8 MHz X’tal OSC IN.
VDD1 = 1.0 V to 1.1 V
VDD2 = 2.85 V to 3.15 V
No Input Signal, VDD1 = 1.1 V
EO, EOP pin. VDD2 = 2.85 V
VOH = VDD2 ð0.5 V
XO pin. VOH = VDD1 ð0.5 V
FR pin. VOH = VDD1 ð0.5 V
EO, EON pin. VDD2 = 2.85 V
VOL = 0.5 V
XO pin. VOL = 0.5 V
FR pin. VOL = 0.5 V
FIN, XI pin. VIH = VDD1 1.0 V
FIN, XI pin. VIL = 0 V, VDD1 1.0 V
DATA, CLK, LE, PS pin. VIH1 = 3.85 V
DATA, CLK, LE, PS pin.
DATA, CLK, LE, PS pin.
RESET pin.
RESET pin.
EO, EOP, EON pin.
VDD1 = 1.0 V to 1.1 V
VDD2 = 2.85 V to 3.15 V
AC PERFORMANCE (Unless otherwise specified, VDD1 = 1.00 V to 1.15 V, VDD2 = 2.70 to 3.30 V, TA = ð10 to +50 qC)
PARAMETER
Input frequency 1
Input frequency 2
SYMBOL
fin1
fin2
MIN.
10
10
Reference Oscillating Frequency
fx’tal
TYP.
12.8
MAX.
70
94
UNIT
MHz
MHz
MHz
CONDITIONS
FIN pin, Vin = 0.2 VP-P
FIN pin, Vin = 0.2 VP-P,
VDD1 = 1.05 V to 1.15 V
XI, XO pin
5