UPD77015 Datasheet, PDF (43/60 Pages) NEC – 16 bits, Fixed-point Digital Signal Processor

µPD77015, 77017, 77018
Serial Interface
Required Timing Condition
Parameters
SCK input cycle time
SCK input high/low level width
SCK input rise/fall time
SOEN recovery time
SOEN hold time
SIEN recovery time
SIEN hold time
SI setup time
SI hold time
Symbol
tcSC
twSC
trfSC
trecSOE
thSOE
trecSIE
thSIE
tsuSI
thSI
Conditions
MIN.
2tcC
25
20
0
20
0
20
0
TYP.
MAX.
Unit
ns
ns
20
ns
ns
ns
ns
ns
ns
ns
Switching Characteristics
Parameters
SORQ output delay time
SORQ hold time
SO valid time
SO hold time
SIAK output delay time
SIAK hold time
Symbol
tdSOR
thSOR
tvSO
thSO
tdSIA
thSIA
Conditions
MIN.
0
0
0
TYP.
MAX.
Unit
30
ns
ns
30
ns
ns
30
ns
ns
Notes for Serial Clock
Serial clock inputs SCK1 and SCK2 are sensitive to any kind of interfering signals (noise on power supply,
induced voltage, etc.). Spurious signals can cause malfunction of the device. Special care for the serial clock
design should be taken. Careful grounding, decoupling and short wiring of SCK1 and SCK2 are recommended.
Intersection of SCK1 and SCK2 with other serial interface lines or close wiring to lines carrying high frequency
signals or large changing currents should be avoided.
It considers for the serial clock to make a waveform stable especially about the rising and falling.
Example 1. good example
Straight rising form and falling
form
Example 2. no good example
It doesn’t bound. It doesn’t make
noise one above another.
Example 3. no good example
It doesn’t make a stair stepping.
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