UPD8821 Datasheet, PDF (4/24 Pages) NEC – 7300 PIXELS × 3 COLOR CCD LINEAR IMAGE SENSOR

μ PD8821
ABSOLUTE MAXIMUM RATINGS (TA = +25°C)
Parameter
Symbol
Ratings
Unit
Output drain voltage
VOD
–0.3 to +12.0
V
Heat sink voltage
HS-VOD
–0.3 to +12.0
V
Shift register clock voltage
Vφ 1, Vφ 2
–0.3 to +8.0
V
Last stage shift register clock voltage
Vφ 2L
–0.3 to +8.0
V
Reset gate clock voltage
Vφ R
–0.3 to +8.0
V
Reset feed-through level clamp clock voltage
Vφ CP
–0.3 to +8.0
V
Transfer gate clock voltage
Operating ambient temperature ^Note
Vφ TG1 to Vφ TG3
–0.3 to +8.0
V
TA
0 to +60
˚C
Storage temperature
Tstg
–40 to +100
˚C
Note The operating ambient temperature is defined as an atmosphere temperature in a point 10 mm away on the
substrate, and 10 mm away from the short side of package 1 pin.
Caution
Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the
verge of suffering physical damage, and therefore the product must be used under conditions that
ensure that the absolute maximum ratings are not exceeded.
RECOMMENDED OPERATING CONDITIONS (TA = +25°C)
Parameter
Symbol
MIN.
TYP.
MAX.
Unit
Output drain voltage
VOD
9.5
10.0
10.5
V
Heat sink voltage
HS-VOD
9.5
10.0
10.5
V
Shift register clock high level
Vφ 1H, Vφ 2H
4.75
5.0
6.0
V
Shift register clock low level
Vφ 1L, Vφ 2L
–0.3
0.0
+0.25
V
Last stage shift register clock high level
Vφ 2LH
4.75
5.0
6.0
V
Last stage shift register clock low level
Vφ 2LL
–0.3
0.0
+0.25
V
Reset gate clock high level
Vφ RH
4.75
5.0
5.5
V
Reset gate clock low level
Vφ RL
-0.3
0.0
+0.5
V
Reset feed-through level clamp clock high level
Vφ CPH
4.75
5.0
6.0
V
Reset feed-through level clamp clock low level
Transfer gate clock high level ^Note
Vφ CPL
–0.3
0.0
+0.5
V
Vφ TG1H to Vφ TG3H
4.75
Vφ 1H
Vφ 1H
V
Transfer gate clock low level
Vφ TG1L to Vφ TG3L
–0.3
0.0
+0.5
V
Shift register clock amplitude
Vφ 1p-p, Vφ 2p-p
4.75
5.0
6.3
V
Last stage shift register clock amplitude
Vφ 2Lp-p
4.75
5.0
6.3
V
Reset gate clock amplitude
Vφ Rp-p
4.75
5.0
6.3
V
Reset feed-through level clamp clock amplitude
Vφ CPp-p
4.75
5.0
6.3
V
Transfer gate clock amplitude
Data rate
Vφ TGp-p
2 × fφ R
4.5
5.0
6.3
V
0.2
2
60
MHz
Note When Transfer gate clock high level (Vφ TGH) is higher than shift register clock high level (Vφ 1H), image lag can
increase.
4
Data Sheet S17961EJ2V0DS