UPD3728 Datasheet, PDF (4/24 Pages) NEC – 7300 PIXELS x 3 COLOR CCD LINEAR IMAGE SENSOR

µPD3728
ABSOLUTE MAXIMUM RATINGS (TA = +25 °C)
Parameter
Symbol
Ratings
Unit
Output drain voltage
VOD
–0.3 to +15
V
Shift register clock voltage
Vφ1, Vφ1L, Vφ10, Vφ2, Vφ20
–0.3 to +15
V
Reset gate clock voltage
VφRB
–0.3 to +15
V
Reset feed-through level clamp clock voltage
VφCLB
–0.3 to +15
V
Transfer gate clock voltage
VφTG1 to VφTG3
–0.3 to +15
V
Operating ambient temperature
TA
–25 to +60
°C
Storage temperature
Tstg
–40 to +100
°C
Caution Exposure to ABSOLUTE MAXIMUM RATINGS for extended periods may affect device reliability;
exceeding the ratings could cause permanent damage. The parameters apply independently.
RECOMMENDED OPERATING CONDITIONS (TA = +25 °C)
Parameter
Output drain voltage
Shift register clock high level
Shift register clock low level
Reset gate clock high level
Reset gate clock low level
Reset feed-through level clamp clock high level
Reset feed-through level clamp clock low level
Transfer gate clock high level^Note
Symbol
VOD
Vφ1H, Vφ1LH, Vφ10H, Vφ2H, Vφ20H
Vφ1L, Vφ1LL, Vφ10L, Vφ2L, Vφ20L
VφRBH
VφRBL
VφCLBH
VφCLBL
VφTG1H to VφTG3H
Transfer gate clock low level
Data rate
VφTG1L to VφTG3L
2fφRB
MIN.
11.4
4.5
–0.3
4.5
–0.3
4.5
–0.3
4.5
–0.3
–
TYP.
12.0
5.0
0
5.0
0
5.0
0
Vφ1H
(Vφ10H)
0
2
MAX.
12.6
5.5
+0.5
5.5
+0.5
5.5
+0.5
Vφ1H
(Vφ10H)
+0.5
40
Unit
V
V
V
V
V
V
V
V
V
MHz
Note When Transfer gate clock high level (VφTG1H to VφTG3H) is higher than Shift register clock high level (Vφ1H (Vφ10H)),
Image lag can increase.
Remark Pin 9 (φ10) and pin 28 (φ20) should be open to decrease the influence of input clock noise to output signal
waveform, in case of operating at low or middle speed range; data rate under 24 MHz or so.
4
DATA SHEET S13878EJ1V0DS00