UPD16772A Datasheet, PDF (4/20 Pages) NEC – 480-OUTPUT TFT-LCD SOURCE DRIVER COMPATIBLE WITH 64-GRAY SCALES

µPD16772A
4. PIN FUNCTIONS
Pin Symbol
S1 to S480
D00 to D05
D10 to D15
D20 to D25
D30 to D35
D40 to D45
D50 to D55
R,/L
STHR
STHL
CLK
STB
POL
POL21,
POL22
LPC
Bcont
V0 to V9
VDD1
VDD2
VSS1
VSS2
Pin Name
Driver output
Display data input
Description
The D/A converted 64-gray-scale analog voltage is output.
The display data is input with a width of 36 bits, viz., the gray scale data (6 bits) by 6 dots (2
pixels).
DX0: LSB, DX5: MSB
Shift direction control These refer to the start pulse I/O pins when driver ICs are connected in cascade. The shift
input
directions of the shift registers are as follows.
R,/L = H: STHR input, S1 → S480, STHL output
R,/L = L: STHL input, S480 → S1, STHR output
Right shift start pulse These refer to the start pulse I/O pins when driver ICs are connected in cascade.
input/output
Fetching of display data starts when H is read at the rising edge of CLK.
Left shift start pulse R,/L = H (right shift): STHR input, STHL output
input/output
R,/L = L (left shift): STHL input, STHR output
The start pulse width (H level) for next-level drivers is 1CLK.
Shift clock input
Refers to the shift register’s shift clock input. The display data is incorporated into the data
register at the rising edge. At the rising edge of the 80^th clock after the start pulse input, the
start pulse output reaches the high level, thus becoming the start pulse of the next-level
driver. If 82 clock pulses are input after input of the start pulse, input of display data is halted
automatically. The contents of the shift register are cleared at the STB’s rising edge.
Latch input
The contents of the data register are transferred to the latch circuit at the rising edge. And,
at the falling edge, the gray scale voltage is supplied to the driver. It is necessary to ensure
input of one pulse per horizontal period.
Polarity input
POL = L: The S2n–1 output uses V0 to V4 as the reference supply. The S2n output uses V5 to
V9 as the reference supply.
POL = H: The S2n–1 output uses V5 to V9 as the reference supply. The S2n output uses V0 to
V4 as the reference supply.
S2n–1 indicates the odd output: and S2n indicates the even output. Input of the POL signal is
allowed the setup time(tPOL-STB) with respect to STB’s rising edge.
Data inversion input Data inversion can invert when display data is loaded.
POL21/22 = H : Data inversion loads display data after inverting it.
POL21/22 = L : Data inversion does not invert input data.
POL21: D00 to D05, D10 to D15, D20 to D25
POL22: D30 to D35, D40 to D45, D50 to D55
Low power control
input
The current consumption of VDD2 is lowered by controlling the constant current source of the
output amplifier. This pin is pulled up to the VDD1 power supply inside the IC. For details,
see 9. CURRENT CONSUMPTION REDUCTION FUNCTION.
Bias control
This pin can be used to finely control the bias current inside the output amplifier.
When this fine-control function is not required, leave this pin open. For details, see
9. CURRENT CONSUMPTION REDUCTION FUNCTION.
γ -corrected power
supplies
Input the γ -corrected power supplies from outside by using operational amplifier. Make sure
to maintain the following relationships. During the gray scale voltage output, be sure to keep
the gray scale level power supply at a constant level.
VDD2 − 0.1 V > V0 > V1 > V2 > V3 > V4 > 0.5 VDD2 > V5 > V6 > V7 > V8 > V9 > VSS2 + 0.1 V
Logic power supply 2.3 to 3.6 V
Driver power supply 8.5 V ± 0.5 V
Logic ground
Grounding
Driver ground
Grounding
4
Data Sheet S14725EJ1V0DS00