UPD160061 Datasheet, PDF (4/18 Pages) NEC – 384-OUTPUT TFT-LCD SOURCE DRIVER

µPD160061
4. PIN FUNCTIONS
(1/2)
Pin Symbol
Pin Name
I/O
Description
S1 to S384
D00 to D05
D10 to D15
D20 to D25
D30 to D35
D40 to D45
D50 to D55
R,/L
Driver output
Display data input
Output The D/A converted 64-gray-scale analog voltage is output.
Input The display data is input with a width of 36 bits, viz., the gray scale data (6 bits) by 6 dots (2
pixels).
DX0: LSB, DX5: MSB
Shift direction control
Input
These refer to the start pulse I/O pins when driver ICs are connected in cascade.
Fetching of display data starts when H is read at the rising edge of CLK.
R,/L = H (right shift): STHR input, S1→S384, STHL output
R,/L = L (left shift): STHL input, S384→S1, STHR output
STHR
STHL
CLK
STB
POL
POL21,
POL22
LPC,
HPC
Right shift start pulse
input/output
Left shift start pulse
input/output
Shift clock input
Latch input
Polarity input
Data inversion input
Bias current control
input
I/O
Input
Input
Input
Input
Input
These refer to the start pulse I/O pins when driver ICs are connected in cascade.
Fetching of display data starts when H is read at the rising edge of CLK.
When right shift: STHR input, STHL output
When left shift: STHL input, STHR output
A high level should be input as the pulse of one cycle of the clock signal.
If the start pulse input is more than 2CLK, the first 1CLK of the high-level input is valid.
Refers to the shift register’s shift clock input. The display data is incorporated into the data
register at the rising edge. At the rising edge of the 64th after the start pulse input, the start
pulse output reaches the high level, thus becoming the start pulse of the next-level driver. If
66th clock pulses are input after input of the start pulse, input of display data is halted
automatically. The contents of the shift register are cleared at the STB’s rising edge.
The contents of the data register are transferred to the latch circuit at the rising edge. And, at
the falling edge of the STB, the gray scale voltage is supplied to the driver. When STB = H
period, driver output level is Hi-Z (High impedance).
It is necessary to ensure input of one pulse per horizontal period.
POL = L: The S2n–1 output uses V0 to V4 as the reference supply. The S2n output uses V5 to
V9 as the reference supply.
POL = H: The S2n–1 output uses V5 to V9 as the reference supply. The S2n output uses V0 to
V4 as the reference supply.
S2n-1 indicates the odd output, and S2n indicates the even output. Input of the POL signal is
allowed the setup time (tPOL-STB) with respect to STB’s rising edge.
Data inversion can invert when display data is loaded.
POL21: D00 to D05, D10 to D15, D20 to D25, data inversion can invert display data
POL22: D30 to D35, D40 to D45, D50 to D55, data inversion can invert display data
POL21, POL22 = H: Data inversion loads display data after inverting it.
POL21, POL22 = L: Data inversion does not invert input data.
Please refer to panel loads and driver power supply voltage (VDD2), when set up these pins.
Refer to 10. BIAS CURRENT CONTROL BY LPC AND HPC. LPC pin is pulled down to the
VSS1 inside the IC, HPC pin is pulled up to the VDD1 inside the IC.
4
Data Sheet S15843EJ3V0DS