UPA2790GR Datasheet, PDF (4/11 Pages) NEC – SWITCHING N- AND P-CHANNEL POWER MOS FET

µ PA2790GR
P-channel
CHARACTERISTICS
Zero Gate Voltage Drain Current
Gate Leakage Current
Gate Cut-off Voltage
Forward Transfer Admittance ^Note
Drain to Source On-state Resistance ^Note
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Turn-on Delay Time
Rise Time
Turn-off Delay Time
Fall Time
Total Gate Charge
Gate to Source Charge
Gate to Drain Charge
Body Diode Forward Voltage ^Note
Reverse Recovery Time
Reverse Recovery Charge
Note Pulsed
SYMBOL
TEST CONDITIONS
IDSS
IGSS
VGS(off)
VDS = −30 V, VGS = 0 V
VGS = m16 V, VDS = 0 V
VDS = −10 V, ID = −1 mA
| yfs | VDS = −10 V, ID = −3 A
RDS(on)1 VGS = −10 V, ID = −3 A
RDS(on)2 VGS = −4.5 V, ID = −3 A
RDS(on)3 VGS = −4.0 V, ID = −3 A
Ciss
VDS = −10 V
Coss
VGS = 0 V
Crss
f = 1 MHz
td(on)
VDD = −15 V, ID = −3 A
tr
VGS = −10 V
td(off)
RG = 10 Ω
tf
QG
ID = −6 A
QGS
VDD = −24 V
QGD
VGS = −10 V
VF(S-D) IF = 6 A, VGS = 0 V
trr
IF = 6 A, VGS = 0 V
Qrr
di/dt = 100 A/µs
MIN. TYP. MAX. UNIT
−10 µA
m10 µA
−1.0
−2.5 V
2
S
43 60 mΩ
58 80 mΩ
65 110 mΩ
460
pF
130
pF
77
pF
8.5
ns
4.8
ns
42
ns
19
ns
11
nC
1.7
nC
3.3
nC
0.92
V
21
ns
12
nC
TEST CIRCUIT 1 AVALANCHE CAPABILITY
D.U.T.
RG = 25 Ω
L
PG.
50 Ω
VDD
VGS = −20 → 0 V
−
IAS ^BVDSS
VDS
ID
VDD
Starting Tch
TEST CIRCUIT 2 SWITCHING TIME
D.U.T.
RG
PG.
VGS(−)
0
τ
τ = 1 µs
Duty Cycle ≤ 1%
RL
VDD
VGS(−)
VGS
Wave Form
10%
0
VDS(−)
90%
VDS
VDS
Wave Form ⁰
td(on)
VGS
90%
90%
10% 10%
tr td(off)
tf
ton
toff
TEST CIRCUIT 3 GATE CHARGE
D.U.T.
IG = −2 mA
RL
PG.
50 Ω
VDD
4
Data Sheet G16954EJ2V0DS