UPD17933 Datasheet, PDF (34/252 Pages) NEC – 4-BIT SINGLE-CHIP MICROCONTROLLERS WITH DIGITAL TUNING SYSTEM HARDWARE

µPD17933, 17934
Figure 4-2. Configuration of Data Memory
Column address
0 1 2 3 4 5 6 7 8 9 ABCDEF
0
1
2
3
Data memory
4
5
6
BANK0
7
BANK1
BANK2
…
BANK14
BANK15
System registers
BANK0
Column address
0 1 2 3 4 5 6 7 8 9 ABCDEF
0
Data buffer
1
2
3
General registers
4
5
6
7 Port register^{Note 1}
System registers (SYSREG)^{Note 2}
BANK1-BANK2
Column address
0 1 2 3 4 5 6 7 8 9 ABCDEF
0
1
2
3
4
5
6
7 Port register^{Note 3}
System registers (SYSREG)^{Note 2}
BANK3
Column address
0 1 2 3 4 5 6 7 8 9 ABCDEF
0
1
2
3
4
5
6
7 Fixed to 0
System registers (SYSREG)^{Note 2}
BANK14
Column address
0 1 2 3 4 5 6 7 8 9 ABCDEF
0
1
2
Unmounted
3
4
5
6
LCD segment register
7 Fixed to 0
System registers (SYSREG)^{Note 2}
BANK15
Column address
0 1 2 3 4 5 6 7 8 9 ABCDEF
0
1
Control register
2
3
4
Fixed to 0
5
6
Port input/output selection registers
7 Fixed to 0
System registers (SYSREG)^{Note 2}
Notes 1. The high-order 2 bits of 70H are fixed to 0.
2. The same system register exists.
3. Address 71H of BANK1, and the high-order 1 bit and address 73H of BANK2 are fixed to 0.
Cautions 1. Never write anything to address 31H of BANK15 because this address is a test mode area.
2. Address 5BH is not provided to BANK4 through BANK14.
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