UPD70F3040 Datasheet, PDF (33/44 Pages) NEC – V850/SV1TM 32-/16-BIT SINGLE-CHIP MICROCONTROLLERS

µPD70F3040, 70F3040Y
3-Wire SIO Timing
(1) Master Mode (TA = –40 to +85°C, VDD = AVDD = BVDD = 2.7 to 3.6 V, VSS = AVSS = BVSS = 0 V)
Parameter
SCKn cycle time
SCKn high-level width
SCKn low-level width
SIn setup time (to SCKn↑)
SIn hold time (from SCKn↓)
Delay time from SCKn↓ to SOn output
Symbol
tKCY1
<60>
tKH1
<61>
tKL1
<62>
tSIK1
<63>
tKSI1
<64>
tKSO1
<65>
Conditions
MIN.
MAX.
Unit
400
ns
140
ns
140
ns
50
ns
50
ns
60
ns
Remark n = 0 to 3
(2) Slave Mode (TA = –40 to +85°C, VDD = AVDD = BVDD = 2.7 to 3.6 V, VSS = AVSS = BVSS = 0 V)
Parameter
SCKn cycle time
SCKn high-level width
SCKn low-level width
SIn setup time (to SCKn↑)
SIn hold time (from SCKn↓)
Delay time from SCKn↓ to SOn output
Symbol
tKCY2
<60>
tKH2
<61>
tKL2
<62>
tSIK2
<63>
tKSI2
<64>
tKSO2
<65>
Conditions
MIN.
MAX.
Unit
400
ns
140
ns
140
ns
50
ns
50
ns
60
ns
Remark n = 0 to 3
SCKn (I/O)
SIn (input)
SOn (output)
<60>
<61>
<62>
<63> <64>
<65>
Remark n = 0 to 3
Preliminary Data Sheet U14622EJ1V0DS00
33