UPG506B Datasheet, PDF (3/4 Pages) NEC – 14 GHz DIVIDE-BY-8 DYNAMIC PRESCALER

UPG506B
TEST CIRCUITS
CONFIGURATION 1
2 Bias Supply
Zo = 50 Ω
IN
VSS2
(-2.2 V)
10 µF
C
5 IN
See Note 1
6 VGG1
OPEN
7 VGG2
OPEN
8 VSS2
C
VDD 4
NC 3
VSS1 2
OPEN
OUT 1
VDD
C
10 µF
(3.8 V)
VSS1 (0 V) GND
C Zo = 50 Ω
OUT
VDD = 3.8 V
VSS1 = 0 V (GND)
VSS2 = –2.2 V
C: 1000 - 5000 pF Chip Capacitor
CONFIGURATION 2
Single Positive Bias Supply
Zo = 50 Ω ^C
IN
See Note 1
OPEN
GND (0 V) VSS2
OPEN
5 IN
VDD 4
6 VGG1
7 VGG2
NC 3
VSS1 2
OPEN
8 VSS2 OUT 1
C
10 µF
10 µF
*
C
2.2 V
C ^{Zo = 50 Ω}
VDD
(+6 V)
OUT
VDD = +6.0 V
VSS2 = 0 V (GND)
C: 1000 - 5000 pF Chip Capacitor
* VSS1 should be connected to GND through a 2.2 V Zener Diode
(RD2.2FB or IN3394).
CONFIGURATION 3
Single Negative Bias Supply
Zo = 50 Ω
IN
VSS2
(-6 V)
10 µF
C
See Note 1
OPEN
5 IN
6 VGG1
7 VGG2
OPEN
8 VSS2
C
VDD 4
NC 3
VSS1 2
OPEN
OUT 1
10 µF
C
2.2 V
C ^{Zo = 50 Ω}
-6 V*
OUT
VDD = 0 V (GND)
VSS2 = –6 V
C: 1000 - 5000 pF Chip Capacitor
* For VSS1, the bias voltage of -6.0 should be applied through a 2.2 V
Zener Diode (RD2.2FB or IN3394).
Notes:
1. Because of the high internal gain and gain compression of the UPG506B, the device is prone to self-oscillation in the absence of an RF input
signal. This self-oscillation can be suppressed by either of the following means:
• Add a shunt resistor to the RF input line. Typically a resistor value between 50 and 1000 ohms will suppress the self-
oscillation (see the test circuit schematic).
• Apply a negative voltage through a 1000 ohm resistor to the normally open VGG1 connection. Typically voltages between 0
and -9 volts will suppress the self-oscillation.
Both of these approaches will reduce the input sensitivity of the device (by as much as 3 dB for a 50 ohm shunt resistor), but otherwise have no
effect on the reliability or electrical characteristics of the device.