UPA505T Datasheet, PDF (3/9 Pages) NEC – N-CHANNEL/P-CHANNEL MOS FET 5-PIN 2 CIRCUITS

µPA505T
SWITCHING TIME MEASUREMENT CIRCUIT AND MEASUREMENT CONDITIONS
(RESISTANCE LOADED)
• N-ch part
RG
PG.
VGS
0
τ
τ = 1 µs
Duty Cycle ≤ 1 %
• P-ch part
DUT
DUT
RG
PG.
0
VGS
τ
τ = 1 µs
Duty Cycle ≤ 1 %
RL
VDD
Gate
Voltage
Waveform
VGS
10 %
0
VGS(on)
90 %
Drain
Current
Waveform
ID
10 %
0
td(on)
90 %
ID
tr
td(off)
90 %
10 %
tf
ton
toff
RL
VDD
VGS
Gate
Voltage
Waveform
10 %
ID
td(on)
VGS(on)
90 %
tr
td(off)
tf
Drain
Current
0
10 %
Waveform
ID
90 %
10 %
90 %
3